On 6/12/05, Patrick McNamara <[EMAIL PROTECTED]> wrote:
> I found one typo in my first pass through. Mind you, I don't know
> Verilog or VHDL so if there is an error in something specific to the
> description language, I may not catch it.
>
> I must say, it is pretty interesting to see the diagram I drew up
> reduced to something I can look at and say "Well, yeah. That is all it
> does."
Well... I must say that that diagram of yours made the job of coding
the verilog simple and straightforward. So, I guess we both had a
good time. :)
>
> Patrick M
>
> <snip>
>
> >// Stage 1
> >
> >// Peform right shift
> >wire [15:0] shift0 = {source_byte, 8'b0} >> rotate;
> >wire [7:0] shift1 = shift0[15:8] | shift[7:0];
> >
> >
> Shouldn't this be: wire [7:0] shift1 = shift0[15:8] | shift0[7:0];
Yes, you are right.
And I wonder if there isn't a better way to do a rotate in verilog
that the synthesizer will make sense of. You know, every time I try
to so something clever with shifters, like manually code a barrel
shifter, I always get a much worse result than if I just use the >> or
<< operator in verilog.
Something in the back of my mind is telling me that there are <<< and
>>> operators in either VHDL or Verilog, but I cannot remember what
they do... and google chokes on that.
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