On 5/14/06, Ray Heasman <[EMAIL PROTECTED]> wrote:


This is one of my problems with the OGA design.. I think it's too much
with too high NRE costs...


I have no problem with the idea of trying to cram a simple 2D design
into a cheap FPGA and selling that as a complete solution.  That was
my ORIGINAL plan, in fact.  We can use OGD1 as the basis for fleshing
out those ideas.

Imagine fitting everything into the XP6 part on OGD1.  I don't know if
that's possible, really, but it would be interesting to try.

Minimum of what we need:

- Video controller
- Memory controller
- Host interface

Cheap things to add:

- Some format conversion (8-bit emulation, for instance)
- Simple bitblt engine (which gives us solid rectangle fill for free)
- Hardware cursor

Slightly more powerful but still relatively cheap:

- Trapezoid fill (subsumes bitblt and rect and adds triangles and lines)
- Fixed-size patterns (limited color tile and stipple fills)
- Planemasks and raster ops

I can keep adding layers on this, but you get the idea.  We do one and
see how big it is, estimating cost of various fabrication methods
(cheap flash-based FPGA being the preferred).  If there's room, add
something.  Lather, rinse, repeat.

I forget what the XP6 costs.  Perhaps someone here remembers.  It's
not very expensive.  But what would be the demand for a card buildable
on this?  Here's what it'd be like:

- Single head (DVI-I with analog and single-link DVI, no TV)
- One DDR400 ram chip (32 megabytes)
- 200 million pixels per second total memory bandwidth
- 32-bit pixels only
- Absolute minimal text-only VGA support
- No VESA support (due to the lack of VGA graphics)
- Acceleration only for bitblt and solid fill
- Not much room for off-screen pixmaps
- Maybe a hardware cursor

I'm not even sure this could fit in the XP6 we've chosen, although
there's probably a bigger (but more expensive) one we could use.
Usually, more integration is less expensive, but with FPGAs, it's the
other way around.  Two small ones are cheaper than one large one.  We
could split the design across two FPGAs for this.
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