On 7/10/06, Diego Sáenz <[EMAIL PROTECTED]> wrote:
I want to start to document the video controler in the wiki. where can i put
the pages? documentation/OGA1/vid_ctrl? or creating a OGA1 page at home of
OGPwiki?
Below are a few lines about svn video controler connections and registers.
I don understand how depth and pixel shift works. It seems that upper bits of
in_fifo_data are not used. Can some one put a example for each valid depth?
Valid depth values are 1, 2, and 4 for 8, 16, and 32 bit.
Look at how the counter causes a word to be dequeued whenever the it
hits 8. For 32 bits, then, the counter will hold values 4 and 8. The
shifter uses shift_count (3 bits), itself shifted left by 5 to make an
8-bit number, and we're shifting a 256 bit number, so we can get to
all 256 bits of the fifo word.
how must be the format of this info?
Which info? The stuff below? I looked it over, and it looks great!
Diego.
-----------------------------------------------------------------
WARNING: This documents are drafts for internal reference only. Change each 'x'
bit in address or registers to '0' for forward compatible software before use
Block: Video controler
connections:
Verilog name bits In/Out Comments
vid_clock 1 In video clock
pci_clock 1 In pci clock
reset 1 In reset video controler *1
This one is the global reset, although that doesn't make much difference.
reg_write_data 32 In register write data *2
reg_write_addr 10 In register write address *2
reg_write 1 In register write *2
req_addr 28 Out request address
req_enq 1 Out request enqueue
req_busy 1 In request busy
in_fifo_data 256 In in fifo data
deq_in_fifo 1 Out dequeue in fifo
out_pixels 128 Out out pixels
out_signals 3 Out out signals
cursor_x 12 Out cursor x
cursor_y 12 Out cursor y
interrupt 1 Out interrupt request
*1:
hardware reset
reset cpu, clear interrupt, and clear the registers:
video_enable, pc_start, cursor_x_start, cursor_y_start and depth
*2:
Interface for program memory and registers
registers and memory are 32 bits words
Read,
Write,
Address Write
Binary Hex dec Strobe Bits Name Comments
From
0000000000b 000h 0 W Video controler program memory
To Each address have a 32 bits cpu
instruction
0111111111b 1FFh 511
1xxxxxx000b 200h 512 W [11:0] cursor_x_start cursor overlay
x pixel start
1xxxxxx001b 201h 513 W [11:0] cursor_y_start cursor overlay
y pixel start
1xxxxxx010b 202h 514 WS clear_int A write clear
interrupt flag during 8 pci clocks
The 8 clocks are just to deal with the fact that we're crossing clock
domains. Same for cpu_reset.
1xxxxxx011b 203h 515 W [2:0] depth video mode
depth (100b = 32 bits)
1xxxxxx100b 204h 516 WS cpu_reset A write reset
cpu during 8 pci clocks
1xxxxxx101b 205h 517 W [8:0] pc_start start address
of video controler program in video controler program memory
1xxxxxx110b 206h 518 W [0] video_enable 1 enables video
generation
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