I found out that the gpl-cver Verilog simulator
http://www.pragmatic-c.com/gpl-cver/
(portage: gplcver) accepts the Samsung memory simulator model. I tried
with Tim's memory controller:
In memctl_test.v:
`ifdef USE_SAMSUNG_SIM
`define M256
`define X16
`define SCC
ddr #(.pwrup_check(1)) ddr0(
.clk(ram_clk_p[0]), .clkb(ram_clk_n[0]), .csb(1'b0), .cke(/*FIXME*/1'b1),
.ba(bank_out), .ad(addr_out),
.rasb(bus_cmd[2]), .casb(bus_cmd[1]), .web(bus_cmd[0]),
.dm(dm_out[1:0]), .dqi(dq[15:0]), .dqs(dqs[1:0]), .qfc());
ddr #(.pwrup_check(1)) ddr1(
.clk(ram_clk_p[1]), .clkb(ram_clk_n[1]), .csb(1'b0), .cke(/*FIXME*/1'b1),
.ba(bank_out), .ad(addr_out),
.rasb(bus_cmd[2]), .casb(bus_cmd[1]), .web(bus_cmd[0]),
.dm(dm_out[3:2]), .dqi(dq[31:16]), .dqs(dqs[3:2]), .qfc());
`endif
To compile:
cver +define+USE_SAMSUNG_SIM memctl_buf.v memctl_cs.v memctl_fsm.v memctl_test.
↳v memctl_top.v ../../fifos/fifo_16.v ../../fifos/async_fifo_16.v
↳k4h561638f_a2_0501.v
However, I haven't gotten any response form the controller. Note that
there is a bug at line 2757 in the memory model. I just commented out
the line, but there should probably be a loop for i = 0 to `nDM-1 around
it.
On 2006-08-24, Timothy Miller wrote:
> We're coming close to having prototype hardware for OGD1 boards, so
> we're working to get pieces of RTL together for board testing. We
> need modules that are just functional enough to test to make sure all
> of the signals on the board are there and working correctly. As of
> now, we have the following:
>
> Some SPI controllers that we need to be sure are finished:
>
> https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/spi_prom/
>
> We should use the simplest one, which I think is Petter's, IIRC.
That should be finished, but I'll do some more testing to be sure.
> And a couple of memory controllers:
[...]
> The one I'm working on is in the "tims" directory. Petter's is the
> other one. I don't know how well-tested his is, but mine's been
> through a bit of simulation. Perhaps some can have a look at both
> controllers and see if there's anything we can learn from both
> designs. But I also need some people to jump on this so we can get
> the RTL ready to go when it's time to test the hardware.
Yes, I think we'll use yours. Mine is lacking the double-data-rate
glue to interface the chips, though maybe I can learn from yours now.
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