> > // 800 X 600 @ 60Hz with a 40.000MHz pixel clock > > module sync_const; > > > > I'm going to have a look at your code tomorrow.
After putting in param instead of specparam, I finally got it to compile, so this new version actually runs! I used "iverilog testModule.v -o testVideo; ./testVideo" to run it. Be forewarned, however; it takes a really, really long time for the vertical to change (with a bunch of printing, it takes a while per horizontal scan). I need to make this synthesizable by removing the initial block, correct? Also, I think my clockx2 is messed up. I am correct in thinking that the data is changed with each clock_2x change of polarity? Besides the clock issues, this *should* work. // 800 X 600 @ 60Hz with a 40.000MHz pixel clock module sync_const; parameter H_ACTIVE = 800, // pixels H_FRONT_PORCH = 40, // pixels H_SYNCH = 128, // pixels H_BACK_PORCH = 88, // pixels H_TOTAL = 1056, // pixels V_ACTIVE = 600, // lines V_FRONT_PORCH = 1, // lines V_SYNCH = 4, // lines V_BACK_PORCH = 23, // lines V_TOTAL = 628; // lines parameter SYNC_DATA_STATE=0, PORCH_DATA_STATE=1, COLOR_DATA_STATE=0; wire clock; wire clock_2x; wire reset; wire [29:0] vidout; reg [29:0] vid_data; //29:20 R, 19:10 G, 9:0 B reg clk; reg [9:0] vert; //current vertical scanline location reg [11:0] horiz; //current pixel in scanline reg [1:0] hstate; //horizontal and vertical states reg [1:0] vstate; //so it is easier to ref them. assign clock=clk; initial begin vert<=0; horiz<=0; clk<=0; hstate<=0; vstate<=0; end always begin #5 clk=~clk; end always @(posedge clk) begin horiz <= horiz + 1; if (horiz>H_TOTAL) begin hstate <= 0; horiz <=0; vert <= vert + 1; end else if (horiz > H_SYNCH + H_FRONT_PORCH + H_ACTIVE) begin hstate <= 3; end else if (horiz > H_FRONT_PORCH + H_ACTIVE) begin hstate <= 2; end else if (horiz > H_ACTIVE) begin hstate <= 1; end //now all the states are correct: //0) Active - White. //1) Front Porch. //2) Sync signal. 0. //3) Back Porch. //Now set up Vert in the same way... if (vert>V_TOTAL) begin hstate <= 0; horiz <=0; vert <=0; vstate <=0; // new frame end else if (vert > V_SYNCH + V_FRONT_PORCH + V_ACTIVE) begin vstate <= 3; end else if (vert > V_FRONT_PORCH + V_ACTIVE) begin vstate <= 2; end else if (vert > V_ACTIVE) begin vstate <= 1; end //now all is ready. //insert here the code to make colors based //on the various values. //example: just sync signals. if (vstate==2) //sync state begin vid_data<=SYNC_DATA_STATE; end if (hstate==2) //sync state begin vid_data<=SYNC_DATA_STATE; end if (hstate==1 || hstate==3) //porch state begin vid_data<=PORCH_DATA_STATE; end if (vstate==1 || vstate==3) //sync state begin vid_data<=PORCH_DATA_STATE; end if (hstate==0 && vstate==0) //draw state begin vid_data<=COLOR_DATA_STATE; end $display("%g time; hstate %d, vstate %d. horiz=%d, vert=%d.\n", $time,hstate,vstate,horiz,vert); end //head0_video_out u0(clock,clock_2x,reset,vidout,,,,,,,); endmodule _______________________________________________ Open-graphics mailing list Open-graphics@duskglow.com http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)