Sorry it took me so long to respond. Your changes are all good. Please check them in.
On 3/11/07, Simon <[EMAIL PROTECTED]> wrote:
In the spirit of the suggestion that changes be posted to their own threads, here are the changes I mentioned earlier in another thread, before I commit them (svn diff is attached): -change the dumpfile in rtl/vid_ctl/test/video_test.v to video_test.vcd to match the source filename
Good idea. Check it in.
-move a $readmemh call to video_test.v from rtl/vid_ctl/RAMB16_S36_36.v; this makes it possible to use a relative path to specify the memory file's location.
This is smart. We'd want to use the RAM block in different places, and we certainly don't want it loading the same data file in every instance.
-rename RAMB16_S36_36.v to RAMB16_S36_S36.v to match the module declaration within
Yeah. This is a quick-and-dirty version of what we'd find in Xilinx unisims, but this one's good because it would be simpler and faster to use for RTL-level simulations. Whoever checked it in in the first place (me?) typo'd the filename. Check this against unisims, if you have a moment.
-add rtl/vid_ctl/test/Makefile, add a target to drivers/lib/video_controller/Makefile to produce 32x32.hex, needed by tests
Awesome. Does this cover all of the other ones that you posted before? I'm sorry I've lost track of things. I have a break from school for 2 weeks. I'll mostly be working for Tech Source, but I can now also dedicate more cycles to this. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Favorite book: The Design of Everyday Things, Donald A. Norman, ISBN 0-465-06710-7 _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
