2007/3/25, Timothy Normand Miller <[EMAIL PROTECTED]>:
On 3/22/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
> Timothy Normand Miller wrote:
> Isn't it more usual to have a load store architecture with 2 address
> operations? OTOH, there are supposed advantages to register set
> processors (no accumulators).
The idea is to have a load-store architecture, except that the "main
memory" is only 512 32-bit words, and the graphics memory is accessed
via I/O ports.
Don't you think you will win 1 or 2 cycles with a specific kind of load/store ?
> > This is also where we need to deal with branches. If the instruction
> > is a branch, the condition needs to be resolved, and the address needs
> > to be fed back to stage (1). This is why RISC processors typically
> > have a delayed branch. The possible branch conditions are reg-value=0
> > and reg-value!=0.
>
> Were you planing to have a skip on condition instruction?
Not as such. Does MIPS have that? (Not to say that we have to be
tied to that.) We COULD have it...
Conditionnal op could avoid few branches and few load/store. If we use
2 or 3 bits for contionnal execution like for conditionnal branchies,
you could win few cycle more.
> > The MIPS processor stays simple by not having any result flags. That
> > is in an x86 processor, math instructions yield carry, zero, negative,
> > and overflow flags (among others). MIPS doesn't do that, because it
> > causes all sorts of challenging dependencies. You're better off using
> > a few extra instructions and having a processor that's simpler and
> > faster for everything else.
>
> Yes, the saving the state beyond the next instruction causes real
> problems. Exception is that if the next instruction is a BRANCH then
> you keep it for another cycle. That allows for multiple way branches.
Speaking of saving state, that reminds me. We could have interrupts.
Having exceptions that are caused by part of the instruction pipeline
complicates things horribly, but we could easily enough allow for
interrupts, as long as they're always initiated from FETCH, and they
never occur right after a branch instruction.
Does interrupt is an absolu necessity ? It complexify everything.
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