Paul Brook wrote:
On Thursday 19 April 2007 00:47, James Richard Tyrer wrote:
Paul Brook wrote:
Really? I'd expect everything to be a single PCI device. DMA controllers
only tend to exist as separate entities on systems where the normal
devices can't be bus-masters. You may implement it as a separate
functional block in the FPGA, but the host system doesn't know or care
about that.
And exactly how will the host system determine if two interrupts come
from one device or from two separate devices?
In general the only way a host can tell where an interrupt came from is to ask
all the devices (in a device specific fashion) and see which one has an
active interrupt.
On high-end systems you may have a 1:1 mapping from device output to host
input IRQ lines, so can determine an IRQ source without having to poll the
individual devices. However as a device designer/driver writer we can not
assume this is the case.
I'm using the term "device" in the same sense as the PCI spec does.
While you could have separate PCI devices for the DMA and video components
this would at best be a strange configuration. Each PCI device requires its
own OS driver, so you would then need some additional mechanism for matching
up and communicating betwee those guest OS drivers. PCI devices are generally
logically independent devices, which may happen to be on the same physical
card/IC.
We should not presume that the card will be plugged into low end
hardware -- a cheep motherboard with AT style interrupt controllers.
My current entertainment is reading Intel: 31305602.pdf a southbridge
chip. So far, I find that it has *8* PCI interrupt inputs for 4 slots.
It runs in both a legacy (non-APIC) mode and APIC mode. In the APIC
mode, each of these interrupts can be routed to a separate hardware
interrupt vector. That would be 2 interrupts per slot if evenly
distributed. IIUC, another common configuration would be to have 3
slots getting 4 interupts and a bridge with the bridge getting 4 interrupts.
I will probably read through this to get a better understanding of it,
but it appears to me that we have no way of determining how many
hardware vectored interrupts the card will have available. So, I still
suggest that we use 2 (or more) and the worst case is that they will all
wind up connected to the same vector, but it would preform better if we
could find more than 1. This would also mean that at the PCI interface
level that we need to be able to disable the interrupts individually for
each IRQ output.
Next question: does the Linux Kernel have support for APICs on Intel
hardware?
I also note that AGP has 2 interrupts. Since the AGP bus is connected
to the northbridge, these would probably be totally independent of the
PCI bus in the APIC mode. In legacy mode, these are connected together,
but there is an interrupt dedicated to the video card.
--
JRT
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