James Richard Tyrer wrote:
James Richard Tyrer wrote:
It appears that the solution to the jitter problem might be to change
the way that we generate the clocks.
Something like this could be used to generate the existing two clocks
plus a third one to drive the pixel clock generators:
http://focus.ti.com/lit/ds/symlink/cdcel937.pdf
This is EEPROM (1K cycles) so it can't be used for the pixel clock
generators.
For the pixel clock generators, the maximum frequency required and
output voltage required are going to be the main parameters to choose
parts.
To add to this. If, we use a frequency synthesizer for the pixel
clocks, it might actually be less expensive since the PLL's phase
detector would operate at a much lower frequency.
The NXP (Phillips) 3xDAC has a maximum frequency of 330MHz as does the
SiI1178. If we are going to use a pixel clock that fast, there aren't
many dot clock generators that are that fast. 200 to 230MHz seems to be
the upper limit for most chips.
I found a Phillips part that we might want to look at:
http://www.nxp.com/pip/PCK12429_3.html
I'm not well today so someone else will have to look at it.
I also found an IDT chip but it is 5 volt.
If we are going to de-jitter, we should probably look at RF parts.
And to ramble on, the other consideration in a frequency synthesizer is
the channel separation. Actually, that is a questionable concept with a
pixel clock generator, since it needs to generate specific but
disparate values (e.g 25.175MHz & 31.5MHz), but we need to have
sufficient counter resolution to generate the needed frequencies. I
think that VGA 60Hz (25.175MHz) is probably the worst so we need to
design for it. In terms of channel spacing, it is 25KHz.
Which appears to mean that the NXP chip wouldn't work. :-(
Something like this:
http://www.analog.com/UploadedFiles/Data_Sheets/ADF4002.pdf
appears to have large enough counters. With 25Mhz clock, 25.175MHHz is
3EF/3E8 (10 bits) and 31.5 MHZ is 7E/64 (less bits).
The Analog chip would be OK and it is inexpensive, but we would also
require a VCO. The VCO would have to be 2x since we need to run it
through a flipflop to get 50% duty cycle So we are looking for 50MHz to
660MHz (plus some extra for tolerances) that would be stable. IIRC,
thee are issues making a stable VCO with that high a infrequency and
that wide a range. An RC VCO would need to be ECL; One with an inductor
wouldn't have enough range -- you would need a 1, 2, 4 & 8 prescaler.
NSM has a VERY low jitter clock generator:
http://www.national.com/ds/LM/LMK03000.pdf
which I think would work. The datasheet is a bit confusing. But, it
appears to have enough bits in the counters. Unfortunately, it is
expensive.
--
JRT
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