Michael Meeuwisse wrote:
On 5 Mar 2008, at 00:12, Michael Meeuwisse wrote:
I don't think so. If I want to divide by 1, I keep on setting the
countdown to zero, thus essentially toggle the output every clock.
Divide by 4 sets the countdown to 2, etc. I did make a typo there,
the cases should be 1, 2, 4, 8, 16, 32, not 1 - 6.
It's late and I stopped thinking. That wasn't a typo.
On 5 Mar 2008, at 00:34, André Pouliot wrote:
Actually to use the ClkFx output with a frequency input below 18MHz
there shouldn't be any feedback present on the dcm.
For the documentation it's in the document ds099.pdf page 88 table 59
for the timing specification for the Digital Frequency synthesizer.
I'm sorry, I don't follow. I don't see it saying anywhere that CLKFB
shouldn't be connected.
It's in the notice number 1 and 2 below the table. What it said
essentially is, if the delay line output is used(clk0 and other) then
the clkin requirement go from minimum 1MHz to 18MHz for correct
operation of the DFS who generate the clkfx output. Since normally in
that kind of situation people use the clk0 toward the clkfb that force
the requirement of 18MHz for the clkin.
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