Le 2014-08-09 14:09, [email protected] a écrit :
Le 2014-08-09 03:10, Troy Benjegerdes a écrit :
I have not looked far enough into lowRISC to see if it's actually
endian-sane.
"The base ISA has been defined to have a little-endian memory system,
with big-endian or
bi-endian as non-standard variants."
I'll have to look closely at the ISA, I wonder how much or RISC-V was
copied from MIPS...
I see that David Patterson is on board so it should be pretty clean,
being the
5th generation of Berkeley RISC designs...
Note that it is an "open" specification but not "free" :
"We cannot guarantee that all RISC-V implementations will be free of
third-party patent
infringements, but we can guarantee we will not attempt to sue a RISC-V
implementor."
Thanks guys for being clear and honest about it :-D
But as soon as I found the description of the variable-size instruction
encoding,
I stopped reading. It's KISS gone wrong...
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