Dieter wrote:
For TRV10 it will almost certainly be less expensive to put as much
functionality into the ASIC as possible and reduce the chip count.
However this will take more design time.
If there is a lump of functionality that will take a lot of design time
but is available as an inexpensive and well documented chip, it might
make sense to use that chip.
There are two competing factors here. To buy a chip obviously costs
money and adding a 500+ connection chip to a board obviously will
increase the board cost. OTOH, making a larger single chip isn't linear
-- double the size and you more than double the cost, and double the
size and interconnects require more than twice the space (so you have to
more than double the chip size). So, it is an optimization problem.
In this case, this chip appears to have a lot of features which would
require extensive design work to equal.
There is also the Plan B approach of trying to find existing chips
that can do what we need without having to build our own ASIC.
Yes, if we could make a system out of existing chips and programmable
logic (CPLDs not FPGAs), it might be less expensive -- you have to
consider the board costs. IIUC, CPLDs can be directly converted to
ASICs without much trouble at least that was the case with regular
(non-complex) PLDs.
--
JRT
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