Hi Eddie,
> On Tue, 2013-02-19 at 18:30 -0800, Eddie Wai wrote:
> > The code seems correct as it make sense to impose the same hardware
> > segment boundary limit on both the blk queue and the DMA code. It would
> > be an easy alternative to simply prevent the shost->dma_boundary from
> > being set to DMA_BIT_MASK(64), but it seems more correct to fix the
> > amd_iommu code itself to detect and handle this max 64-bit mask condition.
Thanks for tracking this problem down. It turns out that this code does
not only exist in the AMD IOMMU driver but also in other ones (Calgary
and GART at least, havn't checked all).
> > --- a/drivers/iommu/amd_iommu.c
> > +++ b/drivers/iommu/amd_iommu.c
> > @@ -1526,11 +1526,14 @@ static unsigned long dma_ops_area_alloc(struct
> > device *dev,
> > unsigned long boundary_size;
> > unsigned long address = -1;
> > unsigned long limit;
> > + unsigned long mask;
> >
> > next_bit >>= PAGE_SHIFT;
> >
> > - boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
> > - PAGE_SIZE) >> PAGE_SHIFT;
Given that there is a BUG_ON() in the iommu-helpers which checks for
!is_power_of_2(boundary_size) I think we can simplify the this macro and
avoid the overflow in a more clever way:
boundary_size = (dma_get_seg_boundary(dev) >> PAGE_SHIFT) + 1;
This should work because dma_get_seg_boundary(dev) really needs to be a
bitmask which becomes a power_of_2 on incrementing.
Regards,
Joerg
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