drivers/gpu/drm/via/via_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
New commits:
commit 72610a391a7d9b72011a41c190caaa51cb471e7d
Author: HuangRan <huangra...@126.com>
Date: Wed Apr 20 15:06:19 2016 +0800
Fix VX900 HDMI port no display issue
Remove the write of bit6 for VGA/SVGA CRT Controller Register 0xFD
(IGA1 Scaling Up and Timing Control). Bit6 of CRTC 0xFD is RO bit
which can't be written. Verfied on VX900 board for HDMI port.
Signed-off-by: Hu, Yi <h...@iscas.ac.cn>
Signed-off-by: Huang, Ran <huangra...@126.com>
diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index fa29270..a50e654 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -468,7 +468,7 @@ void via_load_crtc_pixel_timing(struct drm_crtc *crtc,
struct drm_display_mode *
svga_wcrt_mask(VGABASE, 0x32, 0x00, BIT(2));
}
- svga_wcrt_mask(VGABASE, 0xFD, BIT(5) | BIT(6), BIT(5) | BIT(6));
+ svga_wcrt_mask(VGABASE, 0xFD, BIT(5), BIT(5));
}
/* Load CRTC timing registers */
@@ -484,7 +484,7 @@ void via_load_crtc_timing(struct via_crtc *iga, struct
drm_display_mode *mode)
svga_wcrt_mask(VGABASE, 0x45, 0x00, BIT(0));
/* Disable IGA1 pixel timing */
- svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(6) | BIT(5));
+ svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(5));
}
reg_value = IGA1_HOR_TOTAL_FORMULA(mode->crtc_htotal);
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