https://bugs.freedesktop.org/show_bug.cgi?id=96397
--- Comment #11 from Xavier Bachelot <xav...@bachelot.org> ---
I've reduced the needed changes to both 3d5.6b bit 7 and 3d5.6c bit 0.
Initial registers setting is 3d5.6b = 0x84 and 3d5.6c = 0x01.
Working registers setting is 3d5.6b = 0x04 and 3d5.6c = 0x00.
According to CX700 documentation, the older chipset with doc available :
6b[7:6] is "First Display Channel Clock Mode Selection"
0x: Normal
1x: Division by 2
6c[0] is "LCDCK Source Selection"
0: LCDCK PLL output clock
1: LCDCK PLL reference clock
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