configure.ac | 2
src/via_driver.c | 4 -
src/via_fp.c | 106 +++++++++++++++++++++++++++++++++++++---
src/via_ums.c | 10 +--
src/via_ums.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
5 files changed, 238 insertions(+), 29 deletions(-)
New commits:
commit e13676ee944937030d28dac476369b01446c955e
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:50:14 2017 -0700
Version bumped to 0.6.156
Added DPA (Digital Port Adjustment?) tables copied from VIA
Technologies Chrome IGP DDX code. At this point, only P4M900 chipset
based devices (P4M900, VN896, and CN896 chipsets) are supported, but
more devices will be supported shortly.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index 49065f9..b2433f5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.6.155],
+ [0.6.156],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit 08311a2d608390dbc60910bf9e8d965a9633b6e3
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:44:06 2017 -0700
Added DPA tables for P4M900 family FP I/O adjustment
It is unclear what DPA stands for (Digital Port Adjustment?), but
apparently it exists inside open source VIA Technologies Chrome IGP
DDX code to adjust I/O driver strength and data phase for FP type
interfaces. Typically, there will be several tables per chipset
depending on what the pixel clock range is. The code to facilitate
this came from open source VIA Technologies Chrome IGP DDX code.
Made various small changes to the imported code, but the functionality
is effectively the same. At this point, only P4M900 chipset based
devices (P4M900, VN896, and CN896 chipsets) are supported.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index e6051f8..f349d7d 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -882,6 +882,102 @@ ViaPanelScaleDisable(ScrnInfoPtr pScrn)
ViaCrtcMask(hwp, 0xA2, 0x00, 0xC8);
}
+static int
+viaGetClockRangeIndex(int Clock)
+{
+ if (Clock < VIA_DPA_CLK_30M) {
+ return VIA_DPA_CLK_RANGE_30M;
+ } else if ((Clock >= VIA_DPA_CLK_30M) && (Clock < VIA_DPA_CLK_50M)) {
+ return VIA_DPA_CLK_RANGE_30M_50M;
+ } else if ((Clock >= VIA_DPA_CLK_50M) && (Clock < VIA_DPA_CLK_70M)) {
+ return VIA_DPA_CLK_RANGE_50M_70M;
+ } else if ((Clock >= VIA_DPA_CLK_70M) && (Clock < VIA_DPA_CLK_100M)) {
+ return VIA_DPA_CLK_RANGE_70M_100M;
+ } else if ((Clock >= VIA_DPA_CLK_100M) && (Clock < VIA_DPA_CLK_150M)) {
+ return VIA_DPA_CLK_RANGE_100M_150M;
+ } else {
+ return VIA_DPA_CLK_RANGE_150M;
+ }
+}
+
+static void
+viaLoadDPA(ScrnInfoPtr pScrn, CARD16 diPort, VIADPAPtr pVIADPA)
+{
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaLoadDPA.\n"));
+
+ if (!pVIADPA) {
+ goto exit;
+ }
+
+ switch (diPort) {
+ case VIA_DI_PORT_DVP0:
+ viaDVP0SetAdjustment(pScrn, pVIADPA->dvp0Adjustment);
+ viaDVP0SetClockDriveStrength(pScrn, pVIADPA->dvp0ClockDriveStrength);
+ viaDVP0SetDataDriveStrength(pScrn, pVIADPA->dvp0DataDriveStrength);
+ break;
+ case VIA_DI_PORT_DVP1:
+ viaDVP1SetAdjustment(pScrn, pVIADPA->dvp1Adjustment);
+ viaDVP1SetClockDriveStrength(pScrn, pVIADPA->dvp1ClockDriveStrength);
+ viaDVP1SetDataDriveStrength(pScrn, pVIADPA->dvp1DataDriveStrength);
+ break;
+ case VIA_DI_PORT_FPDPLOW:
+ viaFPDPLowSetAdjustment(pScrn, pVIADPA->fpdpLowAdjustment);
+ break;
+ case VIA_DI_PORT_FPDPHIGH:
+ viaFPDPHighSetAdjustment(pScrn, pVIADPA->fpdpHighAdjustment);
+ break;
+ case (VIA_DI_PORT_FPDPHIGH |
+ VIA_DI_PORT_FPDPLOW):
+ viaFPDPLowSetAdjustment(pScrn, pVIADPA->fpdpLowAdjustment);
+ viaFPDPHighSetAdjustment(pScrn, pVIADPA->fpdpHighAdjustment);
+ break;
+ default:
+ break;
+ }
+
+exit:
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaLoadDPA.\n"));
+}
+
+static void
+viaFPIOAdjustment(ScrnInfoPtr pScrn,
+ int Chipset, CARD16 diPort, int Clock)
+{
+ VIAPtr pVia = VIAPTR(pScrn);
+ VIADPAInfoTablePtr pVIADPAInfoTable;
+ VIADPAPtr pVIADPA;
+ Bool isDPATableExist = FALSE;
+ int clockRangeIndex = 0;
+ int i = 0;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaFPIOAdjustment.\n"));
+
+ for (i = 0; i < NUMBER_VIA_DPA_TABLE; i++) {
+ if (pVia->Chipset == viaDPAIndexTable[i].Chipset) {
+ isDPATableExist = TRUE;
+ break;
+ }
+ }
+
+ if (isDPATableExist) {
+ if (viaDPAIndexTable[i].pFPDPATable) {
+ pVIADPAInfoTable = viaDPAIndexTable[i].pFPDPATable;
+ }
+
+ clockRangeIndex = viaGetClockRangeIndex(Clock);
+
+ /* Write the value to the register. */
+ pVIADPA = pVIADPAInfoTable[clockRangeIndex].pDPASetting;
+ viaLoadDPA(pScrn, diPort, pVIADPA);
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaFPIOAdjustment.\n"));
+}
+
static void
via_fp_create_resources(xf86OutputPtr output)
{
@@ -1015,13 +1111,9 @@ via_fp_mode_set(xf86OutputPtr output, DisplayModePtr
mode,
ViaPanelScaleDisable(pScrn);
}
- switch (pVia->Chipset) {
- case VIA_P4M900:
- viaFPDPLowSetAdjustment(pScrn, 0x08);
- break;
- default:
- break;
- }
+ viaFPIOAdjustment(pScrn,
+ pVia->Chipset, pVIAFP->diPort,
+ adjusted_mode->Clock);
switch (pVia->Chipset) {
case VIA_CX700:
diff --git a/src/via_ums.h b/src/via_ums.h
index 62e03f3..4c964c2 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -139,10 +139,25 @@
#define VIA_ANALOG_DPMS_SUSPEND 0x02
#define VIA_ANALOG_DPMS_OFF 0x03
+#define VIA_DPA_CLK_30M 30000000
+#define VIA_DPA_CLK_50M 50000000
+#define VIA_DPA_CLK_70M 70000000
+#define VIA_DPA_CLK_100M 100000000
+#define VIA_DPA_CLK_150M 150000000
+
#define BIT(x) (1 << x)
+enum {
+ VIA_DPA_CLK_RANGE_30M,
+ VIA_DPA_CLK_RANGE_30M_50M,
+ VIA_DPA_CLK_RANGE_50M_70M,
+ VIA_DPA_CLK_RANGE_70M_100M,
+ VIA_DPA_CLK_RANGE_100M_150M,
+ VIA_DPA_CLK_RANGE_150M,
+};
+
typedef struct ViaPanelMode {
int Width;
int Height;
@@ -291,6 +306,82 @@ union pllparams {
CARD32 packed;
};
+/*
+ * DPA Setting Structure.
+ */
+typedef struct _VIADPA {
+ CARD8 dvp0Adjustment;
+ CARD8 dvp0ClockDriveStrength;
+ CARD8 dvp0DataDriveStrength;
+ CARD8 dvp1Adjustment;
+ CARD8 dvp1ClockDriveStrength;
+ CARD8 dvp1DataDriveStrength;
+ CARD8 fpdpLowAdjustment;
+ CARD8 fpdpHighAdjustment;
+} VIADPARec, *VIADPAPtr;
+
+typedef struct _VIADPAINFOTABLE {
+ CARD32 ClockRangeIndex;
+ VIADPAPtr pDPASetting;
+} VIADPAInfoTableRec, *VIADPAInfoTablePtr;
+
+typedef struct _VIADPAINDEXTABLE {
+ int Chipset;
+
+ VIADPAInfoTablePtr pExtTMDSDPATable;
+ VIADPAInfoTablePtr pFPDPATable;
+} VIA_DPA_INDEX_TABLE;
+
+
+static VIADPARec viaDPAP4M900ClockDefault[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x07, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+static VIADPARec viaDPAP4M900Clock100M150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x01,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+static VIADPARec viaDPAP4M900Clock150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x01, 0x02, 0x01,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+
+static VIADPAInfoTableRec viaDPAFPP4M900[] = {
+ { VIA_DPA_CLK_RANGE_30M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M900ClockDefault},
+ {VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M900Clock100M150M},
+ { VIA_DPA_CLK_RANGE_150M, viaDPAP4M900Clock150M}
+};
+
+
+static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
+// {VIA_CX700, NULL, NULL},
+// {VIA_P4M890, NULL, viaDPAFPP4M890},
+// {VIA_K8M890, NULL, viaDPAFPK8M890},
+ {VIA_P4M900, NULL, viaDPAFPP4M900},
+// {VIA_VX800, NULL, NULL}
+};
+
+
+#define NUMBER_VIA_DPA_TABLE (sizeof(viaDPAIndexTable) /
sizeof(*(viaDPAIndexTable)))
+
/*
* Resets IGA1 hardware.
commit 70b0f87a941d9d8f5c20ba22e0e45f20d531facb
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:19:26 2017 -0700
Added viaDVP1SetAdjustment
This is an inline function.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_ums.h b/src/via_ums.h
index a4f1e41..62e03f3 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -561,6 +561,21 @@ viaDVP1SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8
dataDriveStrength)
}
/*
+ * Sets DVP1 (Digital Video Port 1) adjustment register.
+ */
+static inline void
+viaDVP1SetAdjustment(ScrnInfoPtr pScrn, CARD8 adjustment)
+{
+ /* 3X5.9B[3:0] - DVP1 Adjustment */
+ ViaCrtcMask(VGAHWPTR(pScrn), 0x9B,
+ adjustment, BIT(3) | BIT(2) | BIT(1) | BIT(0));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP1 Adjustment: %d\n",
+ (adjustment & (BIT(3) | BIT(2) |
+ BIT(1) | BIT(0)))));
+}
+
+/*
* Sets DVP1 (Digital Video Port 1) sync polarity.
*/
static inline void
commit 7595c9095d86a4fe8e4ddc4dd6abb7dbfba04cf8
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:17:18 2017 -0700
Added viaDVP0SetAdjustment
This is an inline function.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_ums.h b/src/via_ums.h
index 75a388b..a4f1e41 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -455,6 +455,21 @@ viaDVP0SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8
dataDriveStrength)
}
/*
+ * Sets DVP0 (Digital Video Port 0) adjustment register.
+ */
+static inline void
+viaDVP0SetAdjustment(ScrnInfoPtr pScrn, CARD8 adjustment)
+{
+ /* 3X5.96[3:0] - DVP0 Adjustment */
+ ViaCrtcMask(VGAHWPTR(pScrn), 0x96,
+ adjustment, BIT(3) | BIT(2) | BIT(1) | BIT(0));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP0 Adjustment: %d\n",
+ (adjustment & (BIT(3) | BIT(2) |
+ BIT(1) | BIT(0)))));
+}
+
+/*
* Sets DVP0 (Digital Video Port 0) sync polarity.
*/
static inline void
commit 5bab540727efe79349f57da1161153849661cbbe
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:10:55 2017 -0700
Rename viaFPDPHighSetDelayTap to viaFPDPHighSetAdjustment
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_ums.h b/src/via_ums.h
index 08eb444..75a388b 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -1041,17 +1041,17 @@ viaFPDPHighSetIOPadState(ScrnInfoPtr pScrn, CARD8
ioPadState)
}
/*
- * Sets FPDP (Flat Panel Display Port) High interface delay tap.
+ * Sets FPDP (Flat Panel Display Port) High adjustment register.
*/
static inline void
-viaFPDPHighSetDelayTap(ScrnInfoPtr pScrn, CARD8 delayTap)
+viaFPDPHighSetAdjustment(ScrnInfoPtr pScrn, CARD8 adjustment)
{
- /* 3X5.97[3:0] - FPDP High Delay Tap */
- ViaCrtcMask(VGAHWPTR(pScrn), 0x97, delayTap,
+ /* 3X5.97[3:0] - FPDP High Adjustment */
+ ViaCrtcMask(VGAHWPTR(pScrn), 0x97, adjustment,
BIT(3) | BIT(2) | BIT(1) | BIT(0));
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "FPDP High Delay Tap: %d\n",
- (delayTap & (BIT(3) | BIT(2) |
+ "FPDP High Adjustment: %d\n",
+ (adjustment & (BIT(3) | BIT(2) |
BIT(1) | BIT(0)))));
}
commit 46ec15116a1e2a67c7d3bafc0ede212ef19a0d09
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Wed Jul 19 12:07:35 2017 -0700
Rename viaFPDPLowSetDelayTap to viaFPDPLowSetAdjustment
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index ca67e97..e6051f8 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -1017,7 +1017,7 @@ via_fp_mode_set(xf86OutputPtr output, DisplayModePtr mode,
switch (pVia->Chipset) {
case VIA_P4M900:
- viaFPDPLowSetDelayTap(pScrn, 0x08);
+ viaFPDPLowSetAdjustment(pScrn, 0x08);
break;
default:
break;
diff --git a/src/via_ums.h b/src/via_ums.h
index 4430649..08eb444 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -986,17 +986,17 @@ viaFPDPLowSetIOPadState(ScrnInfoPtr pScrn, CARD8
ioPadState)
}
/*
- * Sets FPDP (Flat Panel Display Port) Low interface delay tap.
+ * Sets FPDP (Flat Panel Display Port) Low adjustment register.
*/
static inline void
-viaFPDPLowSetDelayTap(ScrnInfoPtr pScrn, CARD8 delayTap)
+viaFPDPLowSetAdjustment(ScrnInfoPtr pScrn, CARD8 adjustment)
{
- /* 3X5.99[3:0] - FPDP Low Delay Tap */
+ /* 3X5.99[3:0] - FPDP Low Adjustment */
ViaCrtcMask(VGAHWPTR(pScrn), 0x99,
- delayTap, BIT(3) | BIT(2) | BIT(1) | BIT(0));
+ adjustment, BIT(3) | BIT(2) | BIT(1) | BIT(0));
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "FPDP Low Delay Tap: %d\n",
- (delayTap & (BIT(3) | BIT(2) |
+ "FPDP Low Adjustment: %d\n",
+ (adjustment & (BIT(3) | BIT(2) |
BIT(1) | BIT(0)))));
}
commit c43bf7e6f61dbe5ab162236d0948d5084938349b
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Mon Jul 17 17:35:05 2017 -0500
Made changes to VIAPreInitâs log messages
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_driver.c b/src/via_driver.c
index 52e0cb1..43e923d 100644
--- a/src/via_driver.c
+++ b/src/via_driver.c
@@ -1272,7 +1272,7 @@ VIAPreInit(ScrnInfoPtr pScrn, int flags)
&pVia->exaScratchSize)
? X_CONFIG : X_DEFAULT;
xf86DrvMsg(pScrn->scrnIndex, from,
- "EXA scratch area size is %d kB.\n",
+ "EXA scratch area size is %d KB.\n",
pVia->exaScratchSize);
}
}
@@ -1365,7 +1365,7 @@ VIAPreInit(ScrnInfoPtr pScrn, int flags)
from = xf86GetOptValInteger(VIAOptions, OPTION_AGPMEM, &pVia->agpMem)
? X_CONFIG : X_DEFAULT;
xf86DrvMsg(pScrn->scrnIndex, from,
- "Will try to allocate %d kB of AGP memory.\n", pVia->agpMem);
+ "Will try to allocate %d KB of AGP memory.\n", pVia->agpMem);
pVIADisplay = pVia->pVIADisplay;
pVIADisplay->TVDotCrawl = FALSE;
commit f057b88668acb4430a1dcdf8cbfaf0f0f4d414b1
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Mon Jul 17 16:23:28 2017 -0500
Made changes to viaMapMMIOâs log messages
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_ums.c b/src/via_ums.c
index 02b004b..e3f37af 100644
--- a/src/via_ums.c
+++ b/src/via_ums.c
@@ -108,7 +108,7 @@ viaMapMMIO(ScrnInfoPtr pScrn)
#endif
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Mapping MMIO at address 0x%lX with "
+ "Mapping MMIO at address 0x%lx with "
"size %u KB.\n",
pVia->MmioBase, VIA_MMIO_REGSIZE / 1024);
@@ -137,7 +137,7 @@ viaMapMMIO(ScrnInfoPtr pScrn)
#endif
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Mapping 2D Host BitBLT space at address 0x%lX with "
+ "Mapping 2D Host BitBLT space at address 0x%lx with "
"size %u KB.\n",
pVia->MmioBase + VIA_MMIO_BLTBASE, VIA_MMIO_BLTSIZE / 1024);
@@ -185,7 +185,7 @@ viaMapMMIO(ScrnInfoPtr pScrn)
#endif
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Mapping the frame buffer at address 0x%lX with "
+ "Mapping the frame buffer at address 0x%lx with "
"size %lu KB.\n",
pVia->FrameBufferBase, pVia->videoRambytes / 1024);
@@ -237,10 +237,6 @@ viaMapMMIO(ScrnInfoPtr pScrn)
pVia->FBFreeStart = 0;
pVia->FBFreeEnd = pVia->videoRambytes;
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Frame buffer start address: %p, free start: 0x%X end: 0x%X\n",
- pVia->FBBase, pVia->FBFreeStart, pVia->FBFreeEnd);
-
#ifdef HAVE_PCIACCESS
if (pVia->Chipset == VIA_VX900) {
pScrn->memPhysBase = pVia->PciInfo->regions[2].base_addr;
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