configure.ac | 2 -
src/via_fp.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++---
2 files changed, 80 insertions(+), 5 deletions(-)
New commits:
commit 33abe730d27ceef08cbd047ccf9647fcd0db53aa
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Jan 6 21:04:05 2018 -0600
Version bumped to 0.6.168
Added K8M890 chipset FP adjustment parameters.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index 258dda3..b3631b8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.6.167],
+ [0.6.168],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit c2e5053129821906d6de93bf2d9a4c8b3e8ebd02
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Jan 6 21:02:40 2018 -0600
Updated via_fp.c copyright notice
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index 6b83d24..f1ba89b 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -1,9 +1,9 @@
/*
- * Copyright 2017 Kevin Brace. All Rights Reserved.
+ * Copyright 2017-2018 Kevin Brace. All Rights Reserved.
* Copyright 2007-2015 The OpenChrome Project
* [https://www.freedesktop.org/wiki/Openchrome]
- * Copyright 1998-2007 VIA Technologies, Inc. All Rights Reserved.
- * Copyright 2001-2007 S3 Graphics, Inc. All Rights Reserved.
+ * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
commit 550d2bfd0438bdd13b630c624a8d74bbd512b6ac
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Jan 6 20:57:45 2018 -0600
Added K8M890 chipset FP adjustment parameters
This helps the mode setting when resuming from standby. The adjustment
data was borrowed from VIA Technologies Chrome IGP DDX source code.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index 564f56e..6b83d24 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -69,6 +69,80 @@ static ViaPanelModeRec ViaPanelNativeModes[] = {
#define MODESUFFIX 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,FALSE,FALSE,0,NULL,0,0.0,0.0
+/*
+ * K8M890 chipset FP DPA parameters default setting.
+ */
+static VIADPARec viaDPAK8M890ClockDefault[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x04, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x04}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 50 MHz
+ * but below 70 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock50M70M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x06, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 70 MHz
+ * but below 100 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock70M100M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x02, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 100 MHz
+ * but below 150 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock100M150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x02, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/* K8M890 Chipset FP DPA (Digital Panel Adjustment?) Table */
+static VIADPAInfoTableRec viaDPAFPK8M890[] = {
+ { VIA_DPA_CLK_RANGE_30M, viaDPAK8M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_30M_50M, viaDPAK8M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_50M_70M, viaDPAK8M890Clock50M70M},
+ { VIA_DPA_CLK_RANGE_70M_100M, viaDPAK8M890Clock70M100M},
+ { VIA_DPA_CLK_RANGE_100M_150M, viaDPAK8M890Clock100M150M},
+ { VIA_DPA_CLK_RANGE_150M, viaDPAK8M890Clock150M}
+};
+
+
static VIADPARec viaDPAP4M900ClockDefault[] = {
/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
@@ -105,10 +179,11 @@ static VIADPAInfoTableRec viaDPAFPP4M900[] = {
{ VIA_DPA_CLK_RANGE_150M, viaDPAP4M900Clock150M}
};
+
static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
// {VIA_CX700, NULL, NULL},
// {VIA_P4M890, NULL, viaDPAFPP4M890},
-// {VIA_K8M890, NULL, viaDPAFPK8M890},
+ {VIA_K8M890, NULL, viaDPAFPK8M890},
{VIA_P4M900, NULL, viaDPAFPP4M900},
// {VIA_VX800, NULL, NULL}
};
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