configure.ac | 2
src/via_fp.c | 137 +------------------------------
src/via_fp.h | 254 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 261 insertions(+), 132 deletions(-)
New commits:
commit 31a85ac6c4ebca2701ce42dd6f328c3695208a88
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sun Jan 7 01:51:55 2018 -0600
Version bumped to 0.6.169
Added P4M890 chipset FP adjustment parameters.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index b3631b8..9a9859a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.6.168],
+ [0.6.169],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit fd3044bdd52558069334265af09673bec567ea26
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sun Jan 7 01:48:28 2018 -0600
Added P4M890 chipset FP adjustment parameters
This helps the mode setting when resuming from standby. The adjustment
parameters were copied from VIA Technologies xf86-video-via DDX
v83-44398 source code.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.h b/src/via_fp.h
index adb621e..afce38b 100644
--- a/src/via_fp.h
+++ b/src/via_fp.h
@@ -40,6 +40,83 @@
* xf86-video-via v83-44398 source code.
*/
+
+/*
+ * P4M890 chipset FP DPA parameters default setting.
+ */
+static VIADPARec viaDPAP4M890ClockDefault[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x07, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x08}
+};
+
+/*
+ * P4M890 chipset FP DPA parameters for dot clock at or above 50 MHz
+ * but below 70 MHz.
+ */
+static VIADPARec viaDPAP4M890Clock50M70M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x06, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x08}
+};
+
+/*
+ * P4M890 chipset FP DPA parameters for dot clock at or above 70 MHz
+ * but below 100 MHz.
+ */
+static VIADPARec viaDPAP4M890Clock70M100M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x08}
+};
+
+/*
+ * P4M890 chipset FP DPA parameters for dot clock at or above 100 MHz
+ * but below 150 MHz.
+ */
+static VIADPARec viaDPAP4M890Clock100M150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x01}
+};
+
+/*
+ * P4M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
+ */
+static VIADPARec viaDPAP4M890Clock150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x01, 0x02, 0x02,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x0D}
+};
+
+/*
+ * P4M890 Chipset FP DPA (Digital Panel Adjustment?) Table
+ */
+static VIADPAInfoTableRec viaDPAFPP4M890[] = {
+ { VIA_DPA_CLK_RANGE_30M, viaDPAP4M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M890Clock50M70M},
+ { VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M890Clock70M100M},
+ { VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M890Clock100M150M},
+ { VIA_DPA_CLK_RANGE_150M, viaDPAP4M890Clock150M}
+};
+
+
/*
* K8M890 chipset FP DPA parameters default setting.
*/
@@ -168,7 +245,7 @@ static VIADPAInfoTableRec viaDPAFPP4M900[] = {
static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
// {VIA_CX700, NULL, NULL},
-// {VIA_P4M890, NULL, viaDPAFPP4M890},
+ {VIA_P4M890, NULL, viaDPAFPP4M890},
{VIA_K8M890, NULL, viaDPAFPK8M890},
{VIA_P4M900, NULL, viaDPAFPP4M900},
// {VIA_VX800, NULL, NULL}
commit 81308ca31aecc38eb5d325b947f4f2f84fdda142
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sun Jan 7 01:13:41 2018 -0600
Created via_fp.h
Transferred FP DPA tables from via_fp.c.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index 41dcb25..80dd5ea 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -35,6 +35,7 @@
#include "via_driver.h"
#include <unistd.h>
+#include "via_fp.h"
/* These table values were copied from lcd.c of VIA Frame
* Buffer device driver. */
@@ -68,126 +69,6 @@ static ViaPanelModeRec ViaPanelNativeModes[] = {
#define MODEPREFIX(name) NULL, NULL, name, 0, M_T_DRIVER | M_T_DEFAULT
#define MODESUFFIX 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,FALSE,FALSE,0,NULL,0,0.0,0.0
-
-/*
- * K8M890 chipset FP DPA parameters default setting.
- */
-static VIADPARec viaDPAK8M890ClockDefault[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x04, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x04, 0x04}
-};
-
-/*
- * K8M890 chipset FP DPA parameters for dot clock at or above 50 MHz
- * but below 70 MHz.
- */
-static VIADPARec viaDPAK8M890Clock50M70M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x06, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x04, 0x02}
-};
-
-/*
- * K8M890 chipset FP DPA parameters for dot clock at or above 70 MHz
- * but below 100 MHz.
- */
-static VIADPARec viaDPAK8M890Clock70M100M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x02, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x02, 0x02}
-};
-
-/*
- * K8M890 chipset FP DPA parameters for dot clock at or above 100 MHz
- * but below 150 MHz.
- */
-static VIADPARec viaDPAK8M890Clock100M150M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x02, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x02, 0x02}
-};
-
-/*
- * K8M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
- */
-static VIADPARec viaDPAK8M890Clock150M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x03, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x02, 0x02}
-};
-
-/* K8M890 Chipset FP DPA (Digital Panel Adjustment?) Table */
-static VIADPAInfoTableRec viaDPAFPK8M890[] = {
- { VIA_DPA_CLK_RANGE_30M, viaDPAK8M890ClockDefault},
- { VIA_DPA_CLK_RANGE_30M_50M, viaDPAK8M890ClockDefault},
- { VIA_DPA_CLK_RANGE_50M_70M, viaDPAK8M890Clock50M70M},
- { VIA_DPA_CLK_RANGE_70M_100M, viaDPAK8M890Clock70M100M},
- { VIA_DPA_CLK_RANGE_100M_150M, viaDPAK8M890Clock100M150M},
- { VIA_DPA_CLK_RANGE_150M, viaDPAK8M890Clock150M}
-};
-
-
-static VIADPARec viaDPAP4M900ClockDefault[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x07, 0x00, 0x00,
- 0x03, 0x00, 0x00,
- 0x08, 0x00}
-};
-
-static VIADPARec viaDPAP4M900Clock100M150M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x03, 0x00, 0x01,
- 0x03, 0x00, 0x00,
- 0x08, 0x00}
-};
-
-static VIADPARec viaDPAP4M900Clock150M[] = {
- /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
- * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
- * FPDP Low Adjustment, FPDP High Adjustment */
- { 0x01, 0x02, 0x01,
- 0x03, 0x00, 0x00,
- 0x08, 0x00}
-};
-
-static VIADPAInfoTableRec viaDPAFPP4M900[] = {
- { VIA_DPA_CLK_RANGE_30M, viaDPAP4M900ClockDefault},
- { VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M900ClockDefault},
- { VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M900ClockDefault},
- { VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M900ClockDefault},
- {VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M900Clock100M150M},
- { VIA_DPA_CLK_RANGE_150M, viaDPAP4M900Clock150M}
-};
-
-
-static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
-// {VIA_CX700, NULL, NULL},
-// {VIA_P4M890, NULL, viaDPAFPP4M890},
- {VIA_K8M890, NULL, viaDPAFPK8M890},
- {VIA_P4M900, NULL, viaDPAFPP4M900},
-// {VIA_VX800, NULL, NULL}
-};
-
static DisplayModeRec OLPCMode = {
MODEPREFIX("1200x900"),
57275, 1200, 1208, 1216, 1240, 0,
diff --git a/src/via_fp.h b/src/via_fp.h
new file mode 100644
index 0000000..adb621e
--- /dev/null
+++ b/src/via_fp.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2017-2018 Kevin Brace. All Rights Reserved.
+ * Copyright 2007-2015 OpenChrome Project
+ * [https://www.freedesktop.org/wiki/Openchrome]
+ * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * via_fp.h
+ *
+ * Header file for via_fp.c.
+ */
+
+#ifndef _VIA_FP_H_
+#define _VIA_FP_H_ 1
+
+
+/*
+ * These FP DPA parameters were copied from VIA Technologies
+ * xf86-video-via v83-44398 source code.
+ */
+
+/*
+ * K8M890 chipset FP DPA parameters default setting.
+ */
+static VIADPARec viaDPAK8M890ClockDefault[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x04, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x04}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 50 MHz
+ * but below 70 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock50M70M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x06, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x04, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 70 MHz
+ * but below 100 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock70M100M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x02, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 100 MHz
+ * but below 150 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock100M150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x02, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/*
+ * K8M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
+ */
+static VIADPARec viaDPAK8M890Clock150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x02, 0x02}
+};
+
+/*
+ * K8M890 Chipset FP DPA (Digital Panel Adjustment?) Table
+ */
+static VIADPAInfoTableRec viaDPAFPK8M890[] = {
+ { VIA_DPA_CLK_RANGE_30M, viaDPAK8M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_30M_50M, viaDPAK8M890ClockDefault},
+ { VIA_DPA_CLK_RANGE_50M_70M, viaDPAK8M890Clock50M70M},
+ { VIA_DPA_CLK_RANGE_70M_100M, viaDPAK8M890Clock70M100M},
+ { VIA_DPA_CLK_RANGE_100M_150M, viaDPAK8M890Clock100M150M},
+ { VIA_DPA_CLK_RANGE_150M, viaDPAK8M890Clock150M}
+};
+
+
+/*
+ * P4M900 chipset FP DPA parameters default setting.
+ */
+static VIADPARec viaDPAP4M900ClockDefault[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x07, 0x00, 0x00,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+/*
+ * P4M900 chipset FP DPA parameters for dot clock at or above 100 MHz
+ * but below 150 MHz.
+ */
+static VIADPARec viaDPAP4M900Clock100M150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x03, 0x00, 0x01,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+/*
+ * P4M900 chipset FP DPA parameters for dot clock at or above 150 MHz.
+ */
+static VIADPARec viaDPAP4M900Clock150M[] = {
+ /* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
+ * DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
+ * FPDP Low Adjustment, FPDP High Adjustment */
+ { 0x01, 0x02, 0x01,
+ 0x03, 0x00, 0x00,
+ 0x08, 0x00}
+};
+
+/*
+ * P4M900 Chipset FP DPA (Digital Panel Adjustment?) Table
+ */
+static VIADPAInfoTableRec viaDPAFPP4M900[] = {
+ { VIA_DPA_CLK_RANGE_30M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M900ClockDefault},
+ { VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M900Clock100M150M},
+ { VIA_DPA_CLK_RANGE_150M, viaDPAP4M900Clock150M}
+};
+
+
+static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
+// {VIA_CX700, NULL, NULL},
+// {VIA_P4M890, NULL, viaDPAFPP4M890},
+ {VIA_K8M890, NULL, viaDPAFPK8M890},
+ {VIA_P4M900, NULL, viaDPAFPP4M900},
+// {VIA_VX800, NULL, NULL}
+};
+
+#endif /* _VIA_FP_H_ */
commit 1e8ad657b29d56ca08c30e525a397a73414fe7b7
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Jan 6 22:17:42 2018 -0600
Made small changes to viaFPGetFPInfoScratchPad
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index 952a321..41dcb25 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -829,7 +829,7 @@ viaFPGetFPInfoScratchPad(xf86OutputPtr output)
CARD8 index;
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Entered viaFPGetFPInfoScratchPad.\n"));
+ "Entered %s.\n", __func__));
index = hwp->readCrtc(hwp, 0x3F) & 0x0F;
@@ -846,15 +846,9 @@ viaFPGetFPInfoScratchPad(xf86OutputPtr output)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Flat Panel Native Resolution: %dx%d\n",
pVIAFP->NativeWidth, pVIAFP->NativeHeight);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Flat Panel Dual Edge Transfer: %s\n",
- pVIAFP->useDualEdge ? "On" : "Off");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Flat Panel Output Color Dithering: %s\n",
- pVIAFP->useDithering ? "On (18 bit)" : "Off (24 bit)");
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Exiting viaFPGetFPInfoScratchPad.\n"));
+ "Exiting %s.\n", __func__));
}
static void
commit c909ed5a8609f1268b430528fb3ead227377478c
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Jan 6 22:15:06 2018 -0600
Rename viaLVDSGetFPInfoFromScratchPad
The new function name is viaFPGetFPInfoScratchPad.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_fp.c b/src/via_fp.c
index f1ba89b..952a321 100644
--- a/src/via_fp.c
+++ b/src/via_fp.c
@@ -821,7 +821,7 @@ ViaPanelGetSizeFromEDID(ScrnInfoPtr pScrn, xf86MonPtr pMon,
* Gets the native panel resolution from scratch pad registers.
*/
static void
-viaLVDSGetFPInfoFromScratchPad(xf86OutputPtr output)
+viaFPGetFPInfoScratchPad(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
vgaHWPtr hwp = VGAHWPTR(pScrn);
@@ -829,7 +829,7 @@ viaLVDSGetFPInfoFromScratchPad(xf86OutputPtr output)
CARD8 index;
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Entered viaLVDSGetFPInfoFromScratchPad.\n"));
+ "Entered viaFPGetFPInfoScratchPad.\n"));
index = hwp->readCrtc(hwp, 0x3F) & 0x0F;
@@ -854,7 +854,7 @@ viaLVDSGetFPInfoFromScratchPad(xf86OutputPtr output)
pVIAFP->useDithering ? "On (18 bit)" : "Off (24 bit)");
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Exiting viaLVDSGetFPInfoFromScratchPad.\n"));
+ "Exiting viaFPGetFPInfoScratchPad.\n"));
}
static void
@@ -1299,14 +1299,14 @@ via_fp_detect(xf86OutputPtr output)
/* For FP without I2C bus connection, CRTC scratch pad
* register supplied by the VGA BIOS is the only method
* available to figure out the FP native screen resolution. */
- viaLVDSGetFPInfoFromScratchPad(output);
+ viaFPGetFPInfoScratchPad(output);
status = XF86OutputStatusConnected;
}
} else {
/* For FP without I2C bus connection, CRTC scratch pad
* register supplied by the VGA BIOS is the only method
* available to figure out the FP native screen resolution. */
- viaLVDSGetFPInfoFromScratchPad(output);
+ viaFPGetFPInfoScratchPad(output);
status = XF86OutputStatusConnected;
}
_______________________________________________
Openchrome-devel mailing list
Openchrome-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/openchrome-devel
