drivers/gpu/drm/openchrome/crtc_hw.h | 12 +
drivers/gpu/drm/openchrome/via_crtc.c | 271 +++++++++++++++++++++++++++++++---
drivers/gpu/drm/openchrome/via_drv.h | 2
3 files changed, 261 insertions(+), 24 deletions(-)
New commits:
commit 8717760ef7bf59659019e44bcaf6b96cce145def
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Jan 26 17:02:02 2018 -0800
drm/openchrome: Version bumped to 3.0.59
Fix for HP Pavilion a800n display getting distorted after standby
resume bug.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_drv.h
b/drivers/gpu/drm/openchrome/via_drv.h
index 194b93f3cddf..6ffe92d9ba50 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -34,7 +34,7 @@
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 58
+#define DRIVER_PATCHLEVEL 59
#include <linux/module.h>
commit 505cc8fc397b7cc91da1344089843a8a28fcbb34
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Jan 26 16:56:50 2018 -0800
drm/openchrome: Fix for KM400 family IGA1 display FIFO not being set
Not setting IGA1 display FIFO when mode setting led to HP Pavilion
a800n's display getting distorted after standby resume.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c
b/drivers/gpu/drm/openchrome/via_crtc.c
index 6f24381553f5..c08d68e3ea26 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -539,6 +539,47 @@ static void via_iga1_display_fifo_regs(struct drm_device
*dev,
DRM_DEBUG_KMS("Entered %s.\n", __func__);
switch (dev->pdev->device) {
+ case PCI_DEVICE_ID_VIA_KM400:
+ if ((mode->hdisplay >= 1600) &&
+ (dev_priv->vram_type <= VIA_MEM_DDR_200)) {
+ /* SR17[7:0] */
+ iga->fifo_max_depth = 58;
+
+ /* SR16[7], SR16[5:0] */
+ iga->fifo_threshold = 24;
+
+ /* SR18[7], SR18[5:0] */
+ iga->fifo_high_threshold = 92;
+ } else {
+ /* SR17[7:0] */
+ iga->fifo_max_depth = 128;
+
+ /* SR16[7], SR16[5:0] */
+ iga->fifo_threshold = 112;
+
+ /* SR18[7], SR18[5:0] */
+ iga->fifo_high_threshold = 92;
+ }
+
+ if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
+ if (mode->hdisplay >= 1600) {
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 16;
+ } else {
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 8;
+ }
+ } else {
+ if (mode->hdisplay >= 1600) {
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 40;
+ } else {
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 36;
+ }
+ }
+
+ break;
case PCI_DEVICE_ID_VIA_K8M800:
iga->display_queue_expire_num = 128;
iga->fifo_high_threshold = 296;
@@ -1458,8 +1499,7 @@ via_iga1_crtc_mode_set(struct drm_crtc *crtc,
via_iga1_set_hsync_shift(VGABASE, 0x05);
/* Load FIFO */
- if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
- && (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
+ if (dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266) {
via_iga1_display_fifo_regs(dev, dev_priv, iga, adjusted_mode);
} else if (adjusted_mode->hdisplay == 1024
&& adjusted_mode->vdisplay == 768) {
commit 78d9eb03a84ef3ac2c421db38b9716776dac8864
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Jan 26 16:50:57 2018 -0800
drm/openchrome: Add via_iga*_display_fifo_regs
Discontinue via_load_fifo_regs function in the process.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c
b/drivers/gpu/drm/openchrome/via_crtc.c
index f44268c55ad9..6f24381553f5 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -529,33 +529,213 @@ via_load_vpit_regs(struct via_device *dev_priv)
vga_w(VGABASE, VGA_ATT_W, BIT(5));
}
-static void
-via_load_fifo_regs(struct via_crtc *iga, struct drm_display_mode *mode)
+static void via_iga1_display_fifo_regs(struct drm_device *dev,
+ struct via_device *dev_priv,
+ struct via_crtc *iga,
+ struct drm_display_mode *mode)
{
- u32 queue_expire_num = iga->display_queue_expire_num, reg_value;
- struct via_device *dev_priv = iga->base.dev->dev_private;
- int hor_active = mode->hdisplay, ver_active = mode->vdisplay;
- struct drm_device *dev = iga->base.dev;
+ u32 reg_value;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ switch (dev->pdev->device) {
+ case PCI_DEVICE_ID_VIA_K8M800:
+ iga->display_queue_expire_num = 128;
+ iga->fifo_high_threshold = 296;
+ iga->fifo_threshold = 328;
+ iga->fifo_max_depth = 384;
+ break;
+
+ case PCI_DEVICE_ID_VIA_PM800:
+ iga->display_queue_expire_num = 128;
+ iga->fifo_high_threshold = 32;
+ iga->fifo_threshold = 64;
+ iga->fifo_max_depth = 96;
+ break;
+
+ case PCI_DEVICE_ID_VIA_CN700:
+ iga->display_queue_expire_num = 0;
+ iga->fifo_high_threshold = 64;
+ iga->fifo_threshold = 80;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* CX700 */
+ case PCI_DEVICE_ID_VIA_VT3157:
+ iga->fifo_high_threshold = iga->fifo_threshold = 128;
+ iga->display_queue_expire_num = 124;
+ iga->fifo_max_depth = 192;
+ break;
+
+ /* K8M890 */
+ case PCI_DEVICE_ID_VIA_K8M890:
+ iga->display_queue_expire_num = 124;
+ iga->fifo_high_threshold = 296;
+ iga->fifo_threshold = 328;
+ iga->fifo_max_depth = 360;
+ break;
+
+ /* P4M890 */
+ case PCI_DEVICE_ID_VIA_VT3343:
+ iga->display_queue_expire_num = 32;
+ iga->fifo_high_threshold = 64;
+ iga->fifo_threshold = 76;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* P4M900 */
+ case PCI_DEVICE_ID_VIA_P4M900:
+ iga->fifo_high_threshold = iga->fifo_threshold = 76;
+ iga->display_queue_expire_num = 32;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* VX800 */
+ case PCI_DEVICE_ID_VIA_VT1122:
+ iga->fifo_high_threshold = iga->fifo_threshold = 152;
+ iga->display_queue_expire_num = 64;
+ iga->fifo_max_depth = 192;
+ break;
+
+ /* VX855 */
+ case PCI_DEVICE_ID_VIA_VX875:
+ /* VX900 */
+ case PCI_DEVICE_ID_VIA_VX900_VGA:
+ iga->fifo_high_threshold = iga->fifo_threshold = 320;
+ iga->display_queue_expire_num = 160;
+ iga->fifo_max_depth = 400;
+ default:
+ break;
+ }
/* If resolution > 1280x1024, expire length = 64, else
expire length = 128 */
if ((dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800
|| dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)
- && ((hor_active > 1280) && (ver_active > 1024)))
- queue_expire_num = 16;
+ && ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
+ iga->display_queue_expire_num = 16;
- if (!iga->index) {
- /* Set IGA1 Display FIFO Depth Select */
- reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
- load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
- } else {
- /* Set IGA2 Display FIFO Depth Select */
- reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
- if (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800)
- reg_value--;
- load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
+ /* Set IGA1 Display FIFO Depth Select */
+ reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
+ load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
+
+ /* Set Display FIFO Threshold Select */
+ reg_value = iga->fifo_threshold / 4;
+ load_value_to_registers(VGABASE, &iga->threshold, reg_value);
+
+ /* Set FIFO High Threshold Select */
+ reg_value = iga->fifo_high_threshold / 4;
+ load_value_to_registers(VGABASE, &iga->high_threshold, reg_value);
+
+ /* Set Display Queue Expire Num */
+ reg_value = iga->display_queue_expire_num / 4;
+ load_value_to_registers(VGABASE, &iga->display_queue, reg_value);
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_iga2_display_fifo_regs(struct drm_device *dev,
+ struct via_device *dev_priv,
+ struct via_crtc *iga,
+ struct drm_display_mode *mode)
+{
+ u32 reg_value;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ switch (dev->pdev->device) {
+ case PCI_DEVICE_ID_VIA_K8M800:
+ iga->display_queue_expire_num = 0;
+ iga->fifo_high_threshold = 296;
+ iga->fifo_threshold = 328;
+ iga->fifo_max_depth = 384;
+ break;
+
+ case PCI_DEVICE_ID_VIA_PM800:
+ iga->display_queue_expire_num = 0;
+ iga->fifo_high_threshold = 64;
+ iga->fifo_threshold = 128;
+ iga->fifo_max_depth = 192;
+ break;
+
+ case PCI_DEVICE_ID_VIA_CN700:
+ iga->display_queue_expire_num = 128;
+ iga->fifo_high_threshold = 32;
+ iga->fifo_threshold = 80;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* CX700 */
+ case PCI_DEVICE_ID_VIA_VT3157:
+ iga->display_queue_expire_num = 128;
+ iga->fifo_high_threshold = 32;
+ iga->fifo_threshold = 64;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* K8M890 */
+ case PCI_DEVICE_ID_VIA_K8M890:
+ iga->display_queue_expire_num = 124;
+ iga->fifo_high_threshold = 296;
+ iga->fifo_threshold = 328;
+ iga->fifo_max_depth = 360;
+ break;
+
+ /* P4M890 */
+ case PCI_DEVICE_ID_VIA_VT3343:
+ iga->display_queue_expire_num = 32;
+ iga->fifo_high_threshold = 64;
+ iga->fifo_threshold = 76;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* P4M900 */
+ case PCI_DEVICE_ID_VIA_P4M900:
+ iga->fifo_high_threshold = iga->fifo_threshold = 76;
+ iga->display_queue_expire_num = 32;
+ iga->fifo_max_depth = 96;
+ break;
+
+ /* VX800 */
+ case PCI_DEVICE_ID_VIA_VT1122:
+ iga->display_queue_expire_num = 128;
+ iga->fifo_high_threshold = 32;
+ iga->fifo_threshold = 64;
+ iga->fifo_max_depth = 96;
+ iga->offset.count++;
+ break;
+
+ /* VX855 */
+ case PCI_DEVICE_ID_VIA_VX875:
+ iga->fifo_high_threshold = iga->fifo_threshold = 160;
+ iga->display_queue_expire_num = 320;
+ iga->fifo_max_depth = 200;
+ iga->offset.count++;
+ break;
+
+ /* VX900 */
+ case PCI_DEVICE_ID_VIA_VX900_VGA:
+ iga->fifo_high_threshold = iga->fifo_threshold = 160;
+ iga->display_queue_expire_num = 320;
+ iga->fifo_max_depth = 192;
+ iga->offset.count++;
+ default:
+ break;
}
+ /* If resolution > 1280x1024, expire length = 64, else
+ expire length = 128 */
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800
+ || dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)
+ && ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
+ iga->display_queue_expire_num = 16;
+
+ /* Set IGA2 Display FIFO Depth Select */
+ reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
+ if (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800)
+ reg_value--;
+ load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
+
/* Set Display FIFO Threshold Select */
reg_value = iga->fifo_threshold / 4;
load_value_to_registers(VGABASE, &iga->threshold, reg_value);
@@ -565,8 +745,10 @@ via_load_fifo_regs(struct via_crtc *iga, struct
drm_display_mode *mode)
load_value_to_registers(VGABASE, &iga->high_threshold, reg_value);
/* Set Display Queue Expire Num */
- reg_value = queue_expire_num / 4;
+ reg_value = iga->display_queue_expire_num / 4;
load_value_to_registers(VGABASE, &iga->display_queue, reg_value);
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
}
/* Load CRTC Pixel Timing registers */
@@ -1278,7 +1460,7 @@ via_iga1_crtc_mode_set(struct drm_crtc *crtc,
/* Load FIFO */
if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
&& (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
- via_load_fifo_regs(iga, adjusted_mode);
+ via_iga1_display_fifo_regs(dev, dev_priv, iga, adjusted_mode);
} else if (adjusted_mode->hdisplay == 1024
&& adjusted_mode->vdisplay == 768) {
/* Update Patch Register */
@@ -1590,7 +1772,7 @@ via_iga2_crtc_mode_set(struct drm_crtc *crtc,
/* Load FIFO */
if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
&& (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
- via_load_fifo_regs(iga, adjusted_mode);
+ via_iga2_display_fifo_regs(dev, dev_priv, iga, adjusted_mode);
} else if (adjusted_mode->hdisplay == 1024
&& adjusted_mode->vdisplay == 768) {
/* Update Patch Register */
commit 9b9007198e960d4a3c7119b788bedab07d709402
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Jan 26 16:26:38 2018 -0800
drm/openchrome: Set IGA1 HSYNC Shift register when mode setting
This improves the display behavior after a standby resume. HP Pavilion
a800n (KM400(A) chipset) had display issues if this register was not
set.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/crtc_hw.h
b/drivers/gpu/drm/openchrome/crtc_hw.h
index b172846a2e24..3a4d792b6ba5 100644
--- a/drivers/gpu/drm/openchrome/crtc_hw.h
+++ b/drivers/gpu/drm/openchrome/crtc_hw.h
@@ -94,6 +94,18 @@ static inline void svga_wcrt_mask(void __iomem *regbase, u8
index, u8 data, u8 m
***********************************************************************/
/*
+ * Sets IGA1's HSYNC Shift value.
+ */
+static inline void
+via_iga1_set_hsync_shift(void __iomem *regs, u8 shift_value)
+{
+ /* 3X5.33[2:0] - IGA1 HSYNC Shift */
+ svga_wcrt_mask(regs, 0x33, shift_value, BIT(2) | BIT(1) | BIT(0));
+ DRM_DEBUG_KMS("IGA1 HSYNC Shift: %u\n",
+ (shift_value & 0x07));
+}
+
+/*
* Sets DVP0 (Digital Video Port 0) I/O pad state.
*/
static inline void
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c
b/drivers/gpu/drm/openchrome/via_crtc.c
index c07766c39adf..f44268c55ad9 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -1272,6 +1272,9 @@ via_iga1_crtc_mode_set(struct drm_crtc *crtc,
via_iga1_interlace_mode(VGABASE,
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
+ /* No HSYNC shift. */
+ via_iga1_set_hsync_shift(VGABASE, 0x05);
+
/* Load FIFO */
if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
&& (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
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