UNCLASSIFIED
Gents, we are getting a segmentation fault when trying to join an RCC
worker to an FPGA worker. While we have done this several times before,
in this case the FPGA environment consists of several workers (see
Troy's list below).
The seg fault occurs in OcpiLibraryAssembly.cxx, in the
Asembly::findImplementations function, when trying to create the i1
variable (of type OU::Implementation).
The fault is because the "m_candidates[c.m_ports[1].m_instance][0].impl"
is null. No check is made, presumably because the other side of the
port should have been assigned at this point.
>From debugging, the error occurs between the initial RCC and the first
FPGA worker.
We will continue to look for errors in the XML of course, but are there
any known issues with multiple FPGA workers (in a single bitstream)? If
not and the XML looks good, could you tell me where the implementation
should be created and assigned?
Cheers,
Nigel
===================================================================
>From Troy...
The FPGA includes the following worker chain:
sma0->interpolator->upconverter->fmc150
mockup->downconverter->decimator->128k Buffer->sma1
HDL Container XML:
<HdlContainer>
<Instance Worker="dp" Index="13" Interconnect="pcie"/>
<Instance Worker="dp" Index="14" Interconnect="pcie"/>
<Instance Worker="sma" Index="0" Adapter="dp0"
configure="1"/>
<Instance Name="interp" Index="1"/>
<Instance Name="upconv" Index="2"/>
<Instance Name="fmc" Index="3"/>
<Instance Name="downconv" Index="4"/>
<Instance Name="decimat" Index="5"/>
<Instance Name="rxbuff" Index="6"/>
<Instance Worker="sma" Index="7" Adapter="dp1"
configure="2"/>
<!-- Container's internal connections -->
<Connection>
<Attach Instance="sma0" Interface="message"/>
<Attach Instance="dp0" Interface="wmi"/>
</Connection>
<Connection>
<Attach Instance="sma1" Interface="message"/>
<Attach Instance="dp1" Interface="wmi"/>
</Connection>
<!-- Connect the container's output to the application's input -->
<Connection Name="in" External="producer">
<Attach Instance="sma0" Interface="out"/>
</Connection>
<!-- Connect the container's input to the application's output -->
<Connection Name="out" External="consumer">
<Attach Instance="sma1" Interface="in"/>
</Connection>
</HdlContainer>
HDL Assembly XML:
<HdlAssembly Name="fpga" Language="Verilog">
<Property Name="hasDebugLogic" Parameter="true" Type="Bool"
Default="true"/>
<Instance Worker="interpolator_t0" Name="interp"/>
<Instance Worker="upconv_t0" Name="upconv"/>
<Instance Worker="fmc150_loopback" Name="fmc"/>
<Instance Worker="downconv_t0" Name="downconv"/>
<Instance Worker="decimator_t0" Name="decimat"/>
<Instance Worker="buffer_t0" Name="rxbuff"/>
<Connection Name="in" External="consumer">
<Attach Instance="interp" Interface="data"/>
</Connection>
<Connection>
<Attach Instance="interp" Interface="rslt"/>
<Attach Instance="upconv" Interface="data"/>
</Connection>
<Connection>
<Attach Instance="upconv" Interface="rslt"/>
<Attach Instance="fmc" Interface="dac"/>
</Connection>
<Connection>
<Attach Instance="fmc" Interface="adc"/>
<Attach Instance="downconv" Interface="data"/>
</Connection>
<Connection>
<Attach Instance="downconv" Interface="rslt"/>
<Attach Instance="decimat" Interface="data"/>
</Connection>
<Connection>
<Attach Instance="decimat" Interface="rslt"/>
<Attach Instance="rxbuff" Interface="data"/>
</Connection>
<Connection Name="out" External="producer">
<Attach Instance="rxbuff" Interface="rslt"/>
</Connection>
</HdlAssembly>
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