Signed-off-by: Khem Raj <raj.k...@gmail.com>
---
 meta/classes/insane.bbclass | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/meta/classes/insane.bbclass b/meta/classes/insane.bbclass
index 7791a867f7..fa15460842 100644
--- a/meta/classes/insane.bbclass
+++ b/meta/classes/insane.bbclass
@@ -71,7 +71,7 @@ def package_qa_get_machine_dict(d):
                         "microblaze":  (189,   0,    0,          False,        
 32),
                         "microblazeeb":(189,   0,    0,          False,        
 32),
                         "microblazeel":(189,   0,    0,          True,         
 32),
-                        "riscv":      (243,    0,    0,          True,         
 32),
+                        "riscv32":    (243,    0,    0,          True,         
 32),
                         "riscv64":    (243,    0,    0,          True,         
 64),
                       },
             "linux" : { 
@@ -99,7 +99,7 @@ def package_qa_get_machine_dict(d):
                         "mipsisa64r6":   ( 8,  0,    0,          False,        
 64),
                         "mipsisa64r6el": ( 8,  0,    0,          True,         
 64),
                         "nios2":      (113,    0,    0,          True,         
 32),
-                        "riscv":      (243,    0,    0,          True,         
 32),
+                        "riscv32":    (243,    0,    0,          True,         
 32),
                         "riscv64":    (243,    0,    0,          True,         
 64),
                         "s390":       (22,     0,    0,          False,        
 32),
                         "sh4":        (42,     0,    0,          True,         
 32),
@@ -126,7 +126,7 @@ def package_qa_get_machine_dict(d):
                         "microblaze":  (189,     0,    0,          False,      
   32),
                         "microblazeeb":(189,     0,    0,          False,      
   32),
                         "microblazeel":(189,     0,    0,          True,       
   32),
-                        "riscv":      (243,      0,    0,          True,       
   32),
+                        "riscv32":    (243,      0,    0,          True,       
   32),
                         "riscv64":    (243,      0,    0,          True,       
   64),
                         "sh4":        (  42,     0,    0,          True,       
   32),
                       },
-- 
2.16.2

-- 
_______________________________________________
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core

Reply via email to