From: Fabio Estevam <feste...@denx.de>
Upgrade to U-Boot 2023.01.
Remove the two patches that are now upstream:
e67f34f778ba ("riscv: support building double-float modules")
1dde977518f1 ("riscv: Fix build against binutils 2.38")
Signed-off-by: Fabio Estevam <feste...@denx.de>
---
...1-riscv-fix-build-with-binutils-2.38.patch | 40 -----------------
...iscv32-Use-double-float-ABI-for-rv32.patch | 44 -------------------
meta/recipes-bsp/u-boot/u-boot-common.inc | 2 +-
meta/recipes-bsp/u-boot/u-boot_2022.10.bb | 9 ----
meta/recipes-bsp/u-boot/u-boot_2023.01.bb | 4 ++
5 files changed, 5 insertions(+), 94 deletions(-)
delete mode 100644
meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
delete mode 100644
meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
delete mode 100644 meta/recipes-bsp/u-boot/u-boot_2022.10.bb
create mode 100644 meta/recipes-bsp/u-boot/u-boot_2023.01.bb
diff --git
a/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
b/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
deleted file mode 100644
index 3598329b99..0000000000
---
a/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 26a7f6b1e4c5f715c03e59a623f0d620498b92cf Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.k...@gmail.com>
-Date: Sun, 13 Feb 2022 21:11:31 -0800
-Subject: [PATCH] riscv: fix build with binutils 2.38
-
-From version 2.38, binutils default to ISA spec version 20191213. This
-means that the csr read/write (csrr*/csrw*) instructions and fence.i
-instruction has separated from the `I` extension, become two standalone
-extensions: Zicsr and Zifencei.
-
-The fix is to specify those extensions explicitely in -march. However as
-older binutils version do not support this, we first need to detect
-that.
-
-Fixes
-arch/riscv/lib/cache.c: Assembler messages:
-arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i'
-
-Upstream-Status: Submitted []
-Signed-off-by: Khem Raj <raj.k...@gmail.com>
----
- arch/riscv/Makefile | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/Makefile
-+++ b/arch/riscv/Makefile
-@@ -28,7 +28,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
- CMODEL = medany
- endif
-
--ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
-mabi=$(ABI) \
-+# Newer binutils versions default to ISA spec version 20191213 which moves
some
-+# instructions from the I extension to the Zicsr and Zifencei extensions.
-+toolchain-need-zicsr-zifencei := $(call cc-option-yn,
-march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)_zicsr_zifencei)
-+zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei
-+
-+ARCH_FLAGS =
-march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(zicsr_zifencei-y)
-mabi=$(ABI) \
- -mcmodel=$(CMODEL)
-
- PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
diff --git
a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
b/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
deleted file mode 100644
index 0bf1bef2c9..0000000000
---
a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 66dfe0fa886f6289add06d1af8642ce2b5302852 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.k...@gmail.com>
-Date: Tue, 9 Feb 2021 16:40:12 -0800
-Subject: [PATCH] riscv32: Use double-float ABI for rv32
-
-So it can use libgcc built with OE toolchain
-Fixes
-error: "can't link hard-float modules with soft-float modules"
-
-Signed-off-by: Khem Raj <raj.k...@gmail.com>
-Upstream-Status: Inappropriate [embedded specific]
----
- arch/riscv/Makefile | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/arch/riscv/Makefile
-+++ b/arch/riscv/Makefile
-@@ -5,11 +5,15 @@
-
- ifeq ($(CONFIG_ARCH_RV64I),y)
- ARCH_BASE = rv64im
-- ABI = lp64
-+ ABI = lp64d
-+ ARCH_D = d
-+ ARCH_F = f
- endif
- ifeq ($(CONFIG_ARCH_RV32I),y)
- ARCH_BASE = rv32im
-- ABI = ilp32
-+ ABI = ilp32d
-+ ARCH_D = d
-+ ARCH_F = f
- endif
- ifeq ($(CONFIG_RISCV_ISA_A),y)
- ARCH_A = a
-@@ -24,7 +28,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
- CMODEL = medany
- endif
-
--ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
-+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
-mabi=$(ABI) \
- -mcmodel=$(CMODEL)
-
- PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc
b/meta/recipes-bsp/u-boot/u-boot-common.inc
index 60c77cbec4..22adad80ff 100644
--- a/meta/recipes-bsp/u-boot/u-boot-common.inc
+++ b/meta/recipes-bsp/u-boot/u-boot-common.inc
@@ -12,7 +12,7 @@ PE = "1"
# We use the revision in order to avoid having to fetch it from the
# repo during parse
-SRCREV = "4debc57a3da6c3f4d3f89a637e99206f4cea0a96"
+SRCREV = "62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9"
SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master"
diff --git a/meta/recipes-bsp/u-boot/u-boot_2022.10.bb
b/meta/recipes-bsp/u-boot/u-boot_2022.10.bb
deleted file mode 100644
index 1ae575790c..0000000000
--- a/meta/recipes-bsp/u-boot/u-boot_2022.10.bb
+++ /dev/null
@@ -1,9 +0,0 @@
-require u-boot-common.inc
-require u-boot.inc
-
-SRC_URI += " file://0001-riscv32-Use-double-float-ABI-for-rv32.patch \
- file://0001-riscv-fix-build-with-binutils-2.38.patch \
- "
-
-DEPENDS += "bc-native dtc-native python3-setuptools-native"
-
diff --git a/meta/recipes-bsp/u-boot/u-boot_2023.01.bb
b/meta/recipes-bsp/u-boot/u-boot_2023.01.bb
new file mode 100644
index 0000000000..2eef1e900e
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/u-boot_2023.01.bb
@@ -0,0 +1,4 @@
+require u-boot-common.inc
+require u-boot.inc
+
+DEPENDS += "bc-native dtc-native python3-setuptools-native"
--
2.25.1
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