The BP seems works.
<7>ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver
<6>pxa27x-ohci pxa27x-ohci: PXA27x OHCI
<6>pxa27x-ohci pxa27x-ohci: new USB bus registered, assigned bus number 1
<6>pxa27x-ohci pxa27x-ohci: irq 3, io mem 0x4c000000
<6>usb usb1: configuration #1 chosen from 1 choice
<6>hub 1-0:1.0: USB hub found
<6>hub 1-0:1.0: 3 ports detected
<4>bp is alive
<6>usb 1-3: new full speed USB device using pxa27x-ohci and address 2
<4>usb 1-3: config 1 has an invalid interface number: 13 but max is 2
<4>usb 1-3: config 1 has an invalid interface number: 6 but max is 2
<4>usb 1-3: config 1 has an invalid interface number: 7 but max is 2
<4>usb 1-3: config 1 has no interface number 0
<4>usb 1-3: config 1 has no interface number 1
<4>usb 1-3: config 1 has no interface number 2
<6>usb 1-3: configuration #1 chosen from 1 choice
2008/7/6, GM Zhuo <[EMAIL PROTECTED]>:
>
> On e6,the handshake only do the last (third) step,this step has passed.
> in the drivers/usb/core/hub.c,the driver can't read device descriptor and
> set address,
> I change the gpio config the P3_3 only as GPIO_OUT and not in fuction of
> USB HOST PORT3,change the UP3OCR as 0x03,
> the driver still can't read device descriptor and set address ,but the
> errcode change from -64 as -110
>
Index: linux-2.6.24.1/arch/arm/mach-pxa/Kconfig
===================================================================
--- linux-2.6.24.1.orig/arch/arm/mach-pxa/Kconfig 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/arch/arm/mach-pxa/Kconfig 2008-07-05 13:28:37.000000000
+0800
@@ -138,7 +138,7 @@
endchoice
config EZX_BP
- bool "Baseband Processor control for EZX platform"
+ tristate "Baseband Processor control for EZX platform"
help
This enables control code for the BP (baseband processor) found in
Motorola's EZX smartphone platform.
Index: linux-2.6.24.1/arch/arm/mach-pxa/ezx-bp.c
===================================================================
--- linux-2.6.24.1.orig/arch/arm/mach-pxa/ezx-bp.c 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/arch/arm/mach-pxa/ezx-bp.c 2008-07-05 13:28:37.000000000
+0800
@@ -24,7 +24,7 @@
#include <asm/arch/ezx-bp.h>
/* BP Handshake */
-#define FIRST_STEP 2
+#define FIRST_STEP 3
#define LAST_STEP 3
#define BP_RDY_TIMEOUT 0x000c0000
@@ -64,6 +64,8 @@
}
EXPORT_SYMBOL_GPL(bp_handshake_passed);
+#include <asm/delay.h>
+
static void handshake(void)
{
/* step 1: check MCU_INT_SW or BP_RDY is low (now it is checked in
apboot) */
@@ -103,9 +105,34 @@
else if (step == 3) {
if (pxa_gpio_get_value(bp->gpio_rdy)) {
step++;
+
+ printk("handshake ready\n");
+
+ {
+
+ pxa_gpio_set_value(bp->gpio_aprdy, 1);
+ pxa_gpio_mode(bp->gpio_aprdy | GPIO_OUT);
+ pxa_gpio_set_value(bp->gpio_aprdy, 1);
+
+
+ }
+ if (pxa_gpio_get_value(bp->gpio_rdy)) {
+ printk("still high\n");
+
+ }else{
+ printk("oops\n");
+ }
+ //udelay(1000);
+ if (pxa_gpio_get_value(bp->gpio_rdy)) {
+ printk("still high\n");
+
+ }else{
+ printk("oops\n");
+ }
+
/* FIXME delay_bklight(); */
- pxa_gpio_set_value(bp->gpio_mcu_int_sw, 1);
- printk(KERN_NOTICE "ezx-bp: handshake passed\n");
+ //pxa_gpio_set_value(bp->gpio_mcu_int_sw, 1);
+ //printk(KERN_NOTICE "ezx-bp: handshake passed\n");
}
}
}
@@ -121,18 +148,70 @@
return IRQ_HANDLED;
}
+/*this fragment code to prevent bp_rdy_int reentry*/
+static int bprdy_interrupt_handling = 0;
+int in_bprdy_interrupt(void)
+{
+ return bprdy_interrupt_handling;
+}
+void set_in_bprdy_interrupt(void)
+{
+ bprdy_interrupt_handling = 1;
+#ifdef BVD_DEBUG
+ printk("bprdy handling set\n");
+#endif
+}
+
+void clear_in_bprdy_interrupt(void)
+{
+ bprdy_interrupt_handling = 0;
+#ifdef BVD_DEBUG
+ printk("bprdy handling cleared\n");
+#endif
+}
+
+
+static unsigned long lastJiffies;
+
static irqreturn_t bp_rdy_handler(int irq, void *dev_id)
{
+
+ if (!pxa_gpio_get_value(bp->gpio_rdy)){
+ printk("last is %d,slot %d\n",lastJiffies,jiffies-lastJiffies);
+ return IRQ_HANDLED;
+ }
+
+ lastJiffies=jiffies;
+ if(in_bprdy_interrupt())
+ {
+ printk("in_bprdy_interrupt[%d]\n", in_bprdy_interrupt());
+ return IRQ_HANDLED;
+ }
+
+ printk("in bprdy interrupt\n");
+ set_in_bprdy_interrupt();
+
+ if (bp_handshake_passed()) {
+ if(in_bprdy_interrupt())
+ clear_in_bprdy_interrupt();
+ }else{
+ handshake();
+ if(in_bprdy_interrupt())
+ clear_in_bprdy_interrupt();
+
+ }
+
+ return IRQ_HANDLED;
// struct bp *bp = dev_id;
- DEBUGP("BP rdy irq\n");
+ printk("bp rdy handler\n");
if (!bp_handshake_passed()) {
handshake();
if (bp_handshake_passed()) {
/* FIXME: (test) try to not disable irq_wdi2 and drain battery
*/
- disable_irq(IRQ_GPIO(bp->gpio_wdi2));
+ //disable_irq(IRQ_GPIO(bp->gpio_wdi2));
/* set bp_rdy handle for usb ipc */
- set_irq_type(IRQ_GPIO(bp->gpio_rdy), IRQT_FALLING);
+ //set_irq_type(IRQ_GPIO(bp->gpio_rdy), IRQT_FALLING);
}
}
#ifdef CONFIG_TS0710_MUX_USB
@@ -195,9 +274,19 @@
/* turn on BP */
pxa_gpio_mode(bp->gpio_reset|GPIO_OUT);
pxa_gpio_set_value(bp->gpio_reset, 1);
-
+ lastJiffies=jiffies;
+
+
+ if(!pxa_gpio_get_value(bp->gpio_rdy)){
+ printk("not rdy...\n");
+
+ }
+
+
check_power_off();
handshake();
+
+
return 0;
fail:
@@ -212,7 +301,7 @@
free_irq(IRQ_GPIO(bp->gpio_wdi), bp);
free_irq(IRQ_GPIO(bp->gpio_wdi2), bp);
free_irq(IRQ_GPIO(bp->gpio_rdy), bp);
- kfree(bp);
+
return 0;
}
Index: linux-2.6.24.1/arch/arm/mach-pxa/ezx-e6.c
===================================================================
--- linux-2.6.24.1.orig/arch/arm/mach-pxa/ezx-e6.c 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/arch/arm/mach-pxa/ezx-e6.c 2008-07-05 13:28:37.000000000
+0800
@@ -26,6 +26,224 @@
#include "generic.h"
+
+#define NUM_INIT_REGS 30
+#define USB2V0_MASK 0x00004
+#define IDF_MASK 0x00010
+#define IDG_MASK 0x00020
+#define SE1_MASK 0x00040
+
+
+/*! Enumeration of all registers in the power IC(s) */
+enum
+{
+ POWER_IC_REG_PCAP_FIRST_REG = 0,
+
+ POWER_IC_REG_PCAP_ISR = POWER_IC_REG_PCAP_FIRST_REG, /*!< Interrupt status
regiter. */
+ POWER_IC_REG_PCAP_IMR, /*!< Interrupt mask register. */
+ POWER_IC_REG_PCAP_PSTAT, /*!< Processor status register. */
+ POWER_IC_REG_PCAP_INT_SEL, /*!< Interrupt select register. */
+ POWER_IC_REG_PCAP_SWCTRL, /*!< Switching regulator control
register. */
+ POWER_IC_REG_PCAP_VREG1, /*!< Regulator bank 1 control register. */
+ POWER_IC_REG_PCAP_VREG2, /*!< Regulator bank 2 control register. */
+ POWER_IC_REG_PCAP_AUX_VREG, /*!< Auxiliary regulator control
register. */
+ POWER_IC_REG_PCAP_BATT_DAC, /*!< Battery control register. */
+ POWER_IC_REG_PCAP_ADC1, /*!< AtoD control register. */
+ POWER_IC_REG_PCAP_ADC2, /*!< AtoD result register. */
+ POWER_IC_REG_PCAP_AUD_CODEC, /*!< Audio codec control register. */
+ POWER_IC_REG_PCAP_RX_AUD_AMPS, /*!< Rx audio amplifiers control
register. */
+ POWER_IC_REG_PCAP_ST_DAC, /*!< Stereo DAC control register. */
+ POWER_IC_REG_PCAP_RTC_TOD, /*!< Real Time Clock time of day
register. */
+ POWER_IC_REG_PCAP_RTC_TODA, /*!< RTC time of day alarm register. */
+ POWER_IC_REG_PCAP_RTC_DAY, /*!< RTC day register. */
+ POWER_IC_REG_PCAP_RTC_DAYA, /*!< RTC day alarm register. */
+ POWER_IC_REG_PCAP_MTRTMR, /*!< AtoD monitor timer register. */
+ POWER_IC_REG_PCAP_PWRCTRL, /*!< Power control register. */
+ POWER_IC_REG_PCAP_BUSCTRL, /*!< Connectivity register. */
+ POWER_IC_REG_PCAP_PERIPH, /*!< Peripheral control register. */
+ POWER_IC_REG_PCAP_AUX_VREG_MASK, /*!< Auxiliary regulator mask register. */
+ POWER_IC_REG_PCAP_VENDOR_REV,
+ POWER_IC_REG_PCAP_LOWPWR_CTRL, /*!< Regulator low power control
register. */
+ POWER_IC_REG_PCAP_PERIPH_MASK, /*!< Peripheral control register. */
+ POWER_IC_REG_PCAP_TX_AUD_AMPS, /*!< Tx audio amplifiers control
register. */
+ POWER_IC_REG_PCAP_GP, /*!< General purpose register. */
+ POWER_IC_REG_PCAP_TEST1,
+ POWER_IC_REG_PCAP_TEST2,
+ POWER_IC_REG_PCAP_VENDOR_TEST1,
+ POWER_IC_REG_PCAP_VENDOR_TEST2,
+
+ POWER_IC_REG_PCAP_LAST_REG = POWER_IC_REG_PCAP_VENDOR_TEST2,
+
+ /* End of PCAP registers. Start of EMU One Chip registers. */
+
+ POWER_IC_REG_EOC_FIRST_REG,
+
+ POWER_IC_REG_EOC_INT_STATUS = POWER_IC_REG_EOC_FIRST_REG,
+ POWER_IC_REG_EOC_INT_MASK,
+ POWER_IC_REG_EOC_INT_SENSE,
+ POWER_IC_REG_EOC_POWER_CONTROL_0,
+ POWER_IC_REG_EOC_POWER_CONTROL_1,
+ POWER_IC_REG_EOC_CONN_CONTROL,
+
+ POWER_IC_REG_EOC_LAST_REG = POWER_IC_REG_EOC_CONN_CONTROL,
+
+ /* End of EMU One Chip Registers. Start of Funlight registers. */
+
+ POWER_IC_REG_FL_FIRST_REG,
+
+ POWER_IC_REG_FL_INPUT1 = POWER_IC_REG_FL_FIRST_REG, /* LED0-7 Input
Register */
+ POWER_IC_REG_FL_REGISTER1, /*!< Register 1...empty */
+ POWER_IC_REG_FL_PSC0, /*!< Frequency Prescaler 0 */
+ POWER_IC_REG_FL_PWM0, /*!< PWM Register 0 */
+ POWER_IC_REG_FL_PSC1, /*!< Frequency Prescaler 1 */
+ POWER_IC_REG_FL_PWM1, /*!< PWM Register 1 */
+ POWER_IC_REG_FL_LS0, /*!< LED0-3 Selector */
+ POWER_IC_REG_FL_LS1, /*!< LED4-7 Selector */
+
+ POWER_IC_REG_FL_LAST_REG = POWER_IC_REG_FL_LS1,
+
+ /* End of Funlight Registers */
+
+ POWER_IC_REG_NUM_REGS_PCAP
+};
+
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+/*! No need to read before writing to the register and no need to read from
cache. */
+#define NO_SPECIAL_READ 0x00
+/*! Must read before writing to the register. */
+#define READ_BEFORE_WRITE 0x01
+/*! Read the register contents from cache instead of hardware. */
+#define READ_FROM_CACHE 0x02
+/*! Must read before writing to the register and must read from cache. */
+#define READ_CACHE_BEFORE_WRITE 0x03
+
+
+#define POWER_IC_REG_NUM_REGS POWER_IC_REG_NUM_REGS_PCAP
+
+
+static const unsigned int
power_ic_register_no_write_masks[POWER_IC_REG_NUM_REGS] =
+{
+
+ /* PCAP Registers */
+ 0x01FFFFFF, /* ISR */
+ 0x01840000, /* IMR */
+ 0x01FFFFFF, /* PSTAT */
+ 0x01840000, /* INT_SEL */
+ 0x01000001, /* SWCTRL */
+ 0x00000000, /* VREG1 */
+ 0x00000001, /* VREG2 */
+ 0x00000001, /* AUX_VREG */
+ 0x00010000, /* BATT_DAC */
+ 0x00000000, /* ADC1 */
+ 0x010FFFFF, /* ADC2 */
+ 0x00000000, /* AUD_CODEC */
+ 0x00000000, /* RX_AUD_AMPS */
+ 0x00F00000, /* ST_DAC */
+ 0x01FFFFFF, /* RTC_TOD */
+ 0x00000000, /* RTC_TODA */
+ 0x01FFFFFF, /* RTC_DAY */
+ 0x00000000, /* RTC_DAYA */
+ 0x00000000, /* MTRTMR */
+ 0x00000000, /* PWRCTRL */
+ 0x00FFE000, /* BUSCTRL */
+ 0x00000000, /* PERIPH */
+ 0x01C00001, /* AUX_VREG_MASK */
+ 0x01FFFFFF, /* VENDOR_REV */
+ 0x00000000, /* LOWPWR_CTRL */
+ 0x01F57716, /* PERIPH_MASK */
+ 0x00070000, /* TX_AUD_AMPS */
+ 0x00000000, /* GP_REG */
+ 0x01C00000, /* TEST1 */
+ 0x01FFE000, /* TEST2 */
+ 0x01FFFFFF, /* VENDOR_TEST */
+ 0x01FFFFFF, /* VENDOR_TEST */
+
+ /* EMU Registers */
+ 0x00FFFFFF, /* Interrupt status */
+ 0x00FFF000, /* Interrupt mask */
+ 0x00FFFFFF, /* Interrupt sense */
+ 0x00F3C000, /* Power control 0 */
+ 0x00FFFFC0, /* Power control 1 */
+ 0x00000000, /* Connectivity control */
+
+ /* Funlight Registers */
+ 0x00000000, /* LED0-7 Input Register */
+ 0x00000000, /* Register 1...no one cares */
+ 0x00000000, /* Frequency Prescaler 0 */
+ 0x00000000, /* PWM Register 0 */
+ 0x00000000, /* Frequency Prescaler 1 */
+ 0x00000000, /* PWM Register 1 */
+ 0x00000000, /* LED0-3 Selector */
+ 0x00000000, /* LED4-7 Selector */
+
+};
+
+/*! @brief Table that defines which registers need to be read before written
+ *
+ * A '1' in bit 0 will indicate that the register should be read before being
written and
+ * a '1' in bit 1 will indicate that the register should always be read from
cache instead
+ * of from the hardware. */
+static const unsigned char read_before_write[POWER_IC_REG_NUM_REGS] =
+{
+
+ /* PCAP Registers */
+ NO_SPECIAL_READ, /* ISR */
+ NO_SPECIAL_READ, /* IMR */
+ NO_SPECIAL_READ, /* PSTAT */
+ READ_FROM_CACHE, /* INT_SEL */
+ READ_FROM_CACHE, /* SWCTRL */
+ READ_FROM_CACHE, /* VREG1 */
+ READ_FROM_CACHE, /* VREG2 */
+ READ_FROM_CACHE, /* AUX_VREG */
+ NO_SPECIAL_READ, /* BATT_DAC */
+ READ_BEFORE_WRITE, /* ADC1 */
+ READ_BEFORE_WRITE, /* ADC2 */
+ READ_FROM_CACHE, /* AUD_CODEC */
+ READ_FROM_CACHE, /* RX_AUD_AMPS */
+ READ_FROM_CACHE, /* ST_DAC */
+ READ_BEFORE_WRITE, /* RTC_TOD */
+ READ_FROM_CACHE, /* RTC_TODA */
+ READ_BEFORE_WRITE, /* RTC_DAY */
+ READ_FROM_CACHE, /* RTC_DAYA */
+ READ_FROM_CACHE, /* MTRTMR */
+ READ_FROM_CACHE, /* PWRCTRL */
+ READ_FROM_CACHE, /* BUSCTRL */
+ READ_FROM_CACHE, /* PERIPH */
+ READ_FROM_CACHE, /* AUX_VREG_MASK */
+ NO_SPECIAL_READ, /* VENDOR_REV */
+ READ_FROM_CACHE, /* LOWPWR_CTRL */
+ READ_FROM_CACHE, /* PERIPH_MASK */
+ READ_FROM_CACHE, /* TX_AUD_AMPS */
+ READ_FROM_CACHE, /* GP_REG */
+ NO_SPECIAL_READ, /* TEST1 */
+ NO_SPECIAL_READ, /* TEST2 */
+ NO_SPECIAL_READ, /* VENDOR_TEST */
+ NO_SPECIAL_READ, /* VENDOR_TEST */
+
+ /* EMU Registers */
+ NO_SPECIAL_READ, /* Interrupt status */
+ NO_SPECIAL_READ, /* Interrupt mask */
+ NO_SPECIAL_READ, /* Interrupt sense */
+ NO_SPECIAL_READ, /* Power control 0 */
+ NO_SPECIAL_READ, /* Power control 1 */
+ NO_SPECIAL_READ, /* Connectivity control */
+
+ /* Funlight Registers */
+ READ_FROM_CACHE, /* LED0-7 Input Register */
+ READ_FROM_CACHE, /* Register 1...no one cares about this one */
+ READ_FROM_CACHE, /* Frequency Prescaler 0 */
+ READ_FROM_CACHE, /* PWM Register 0 */
+ READ_FROM_CACHE, /* Frequency Prescaler 1 */
+ READ_FROM_CACHE, /* PWM Register 1 */
+ READ_FROM_CACHE, /* LED0-3 Selector */
+ READ_FROM_CACHE, /* LED4-7 Selector */
+
+};
+
+
extern void ezx_lcd_power(int, struct fb_var_screeninfo *);
extern void ezx_backlight_power(int);
@@ -142,10 +360,85 @@
.pxafb_lcd_power = &ezx_lcd_power,
};
+
+
+
+static const unsigned int tab_init_reg[NUM_INIT_REGS][2] =
+{
+
+ {POWER_IC_REG_PCAP_IMR, 0x1FFFFFF},
+ {POWER_IC_REG_PCAP_INT_SEL, 0x0000000},
+ {POWER_IC_REG_PCAP_SWCTRL, 0x0002EDE},
+ {POWER_IC_REG_PCAP_VREG1, 0x15778E3},
+ {POWER_IC_REG_PCAP_VREG2, 0x0810234},
+
+ {POWER_IC_REG_PCAP_AUX_VREG, 0x1024BEC},
+ {POWER_IC_REG_PCAP_BATT_DAC, 0x0228E00},
+ {POWER_IC_REG_PCAP_ADC1, 0x0200000},
+ {POWER_IC_REG_PCAP_AUD_CODEC, 0x0000800},
+ {POWER_IC_REG_PCAP_RX_AUD_AMPS, 0x0030000},
+
+ {POWER_IC_REG_PCAP_ST_DAC, 0x0099700},
+ {POWER_IC_REG_PCAP_PWRCTRL, 0x0094108},
+ {POWER_IC_REG_PCAP_BUSCTRL, 0x00002A0},
+
+ {POWER_IC_REG_PCAP_AUX_VREG_MASK, 0x0214D48},
+
+ {POWER_IC_REG_PCAP_LOWPWR_CTRL, 0x1D9610C},
+
+ {POWER_IC_REG_PCAP_PERIPH_MASK, 0x0000000},
+ {POWER_IC_REG_PCAP_TX_AUD_AMPS, 0x000E000},
+ {POWER_IC_REG_PCAP_GP, 0x0000107},
+ {POWER_IC_REG_EOC_INT_MASK, 0x0000FFF},
+
+
+ {POWER_IC_REG_EOC_POWER_CONTROL_0, 0x0080000},
+
+ {POWER_IC_REG_EOC_POWER_CONTROL_1, 0x0000006},
+ {POWER_IC_REG_EOC_CONN_CONTROL, 0x0020060},
+ {POWER_IC_REG_FL_INPUT1, 0x0000000},
+ {POWER_IC_REG_FL_REGISTER1, 0x0000000},
+ {POWER_IC_REG_FL_PSC0, 0x0000000},
+
+ {POWER_IC_REG_FL_PWM0, 0x0000080},
+ {POWER_IC_REG_FL_PSC1, 0x0000000},
+ {POWER_IC_REG_FL_PWM1, 0x0000080},
+ {POWER_IC_REG_FL_LS0, 0x0000000},
+ {POWER_IC_REG_FL_LS1, 0x0000000}
+
+};
+
+/*! @brief Returns 1 if given register is a PCAP register */
+#define POWER_IC_REGISTER_IS_PCAP(reg) \
+ (((reg) >= POWER_IC_REG_PCAP_FIRST_REG) && ((reg) <=
POWER_IC_REG_PCAP_LAST_REG))
+
+/*! @brief Returns 1 if given register is an EMU One Chip register */
+#define POWER_IC_REGISTER_IS_EOC(reg) \
+ (((reg) >= POWER_IC_REG_EOC_FIRST_REG) && ((reg) <=
POWER_IC_REG_EOC_LAST_REG))
+
+/*! @brief Returns 1 if given register is a Funlight register */
+#define POWER_IC_REGISTER_IS_FL(reg) \
+ (((reg) >= POWER_IC_REG_FL_FIRST_REG) && ((reg) <=
POWER_IC_REG_FL_LAST_REG))
+
+
+
+
/* PCAP */
static int e6_pcap_init(void)
{
+ int i;
+ for (i = 0; i < NUM_INIT_REGS; i++)
+ {
+ if (POWER_IC_REGISTER_IS_PCAP(tab_init_reg[i][0]))
+ {
+ //printk("ezx pcap write reg %08x value
%08x\n",tab_init_reg[i][0], tab_init_reg[i][1]);
+ ezx_pcap_write (tab_init_reg[i][0], tab_init_reg[i][1]);
+ }
+ }
+
+ printk("init pcap register finish\n");
/* FIXME */
+ #if 0
ezx_pcap_write(PCAP_REG_INT_SEL, 0x0); /* wrong */
ezx_pcap_write(PCAP_REG_SWCTRL, 0x2ee6); /* partially wrong */
ezx_pcap_write(PCAP_REG_VREG1, 0x15778e3); /* wrong */
@@ -157,7 +450,7 @@
ezx_pcap_write(PCAP_REG_LOWPWR, 0x1d9610c);
ezx_pcap_write(PCAP_REG_PERIPH, 0x0); /* wrong */
ezx_pcap_write(PCAP_REG_GP, 0x107); /* probably unnecessary */
-
+#endif
return 0;
}
@@ -234,6 +527,14 @@
static void __init e6_init(void)
{
+ unsigned long begin;
+
+ OSCC = 0x20 | OSCC_OON; // OSD = ~3ms
+
+
+ PCFR = PCFR_DC_EN | PCFR_OPDE;
+ PSLR = 0x05900f00;
+
set_pxa_fb_info(&e6_fb_info);
pxa_set_mci_info(&e6_mci_platform_data);
@@ -243,6 +544,8 @@
i2c_register_board_info(0, e6_i2c_board_info,
ARRAY_SIZE(e6_i2c_board_info));
#endif
+
+
}
MACHINE_START(EZX, "Motorola Ezx Platform")
Index: linux-2.6.24.1/arch/arm/mach-pxa/ezx.c
===================================================================
--- linux-2.6.24.1.orig/arch/arm/mach-pxa/ezx.c 2008-07-05 13:28:32.000000000
+0800
+++ linux-2.6.24.1/arch/arm/mach-pxa/ezx.c 2008-07-06 10:08:45.000000000
+0800
@@ -75,14 +75,29 @@
/* OHCI Controller */
static int ezx_ohci_init(struct device *dev)
{
+#if 0
/* for A780 support (connected with Neptune) */
pxa_gpio_mode(GPIO30_USB_P3_2); /* GPIO30 - USB_P3_2/ICL_TXENB */
pxa_gpio_mode(GPIO31_USB_P3_6); /* GPIO31 - USB_P3_6/ICL_VPOUT */
- pxa_gpio_mode(GPIO90_USB_P3_5); /* GPIO90 - USB_P3_5/ICL_VPIN */
+ pxa_gpio_mode(GPIO_OUT|GPIO90_USB_P3_5); /* GPIO90 -
USB_P3_5/ICL_VPIN */
pxa_gpio_mode(GPIO91_USB_P3_1); /* GPIO91 - USB_P3_1/ICL_XRXD */
pxa_gpio_mode(GPIO56_USB_P3_4); /* GPIO56 - USB_P3_4/ICL_VMOUT */
pxa_gpio_mode(GPIO113_USB_P3_3);/* GPIO113 - USB_P3_3/ICL_VMIN */
- UP3OCR = 0x00000002;
+ pxa_gpio_mode( GPIO_OUT| GPIO113_USB_P3_3);
+ //GPCR(GPIO113_USB_P3_3) = GPIO_bit(GPIO113_USB_P3_3);
+ //pxa_gpio_mode(GPIO_OUT|GPIO113_USB_P3_3);
+#else
+
+ pxa_gpio_mode(GPIO_ALT_FN_3_OUT | 30); /* GPIO30 - USB_P3_2/ICL_TXENB */
+ pxa_gpio_mode(GPIO_ALT_FN_3_OUT | 32); /* GPIO31 - USB_P3_6/ICL_VPOUT */
+ pxa_gpio_mode(GPIO_ALT_FN_2_IN | 90); /* GPIO90 - USB_P3_5/ICL_VPIN */
+ pxa_gpio_mode(GPIO_ALT_FN_2_IN | 91); /* GPIO91 - USB_P3_1/ICL_XRXD */
+ pxa_gpio_mode(GPIO_ALT_FN_1_OUT | 56); /* GPIO56 - USB_P3_4/ICL_VMOUT */
+ pxa_gpio_mode( GPIO_OUT| 113);
+#endif
+ pxa_gpio_set_value(GPIO113_USB_P3_3, 0);
+
+ UP3OCR = 0x00000003;
UHCHR = UHCHR & ~(UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
@@ -94,6 +109,8 @@
.init = ezx_ohci_init,
};
+
+#if 0
/* BP */
static struct ezxbp_config ezxbp_data = {
.gpio_reset = GPIO_BB_RESET,
@@ -102,6 +119,18 @@
.gpio_rdy = GPIO_BP_RDY,
.gpio_mcu_int_sw = GPIO_MCU_INT_SW,
};
+#endif
+
+/* BP */
+static struct ezxbp_config ezxbp_data = {
+ .gpio_reset = 116,
+ .gpio_wdi = 13,
+ .gpio_wdi2 = 3,
+ .gpio_rdy = 0,
+ .gpio_mcu_int_sw = 56,
+ .gpio_aprdy = 96,
+};
+
static struct platform_device ezxbp_device = {
.name = "ezx-bp",
Index: linux-2.6.24.1/drivers/usb/core/hub.c
===================================================================
--- linux-2.6.24.1.orig/drivers/usb/core/hub.c 2008-07-05 13:28:32.000000000
+0800
+++ linux-2.6.24.1/drivers/usb/core/hub.c 2008-07-06 10:39:00.000000000
+0800
@@ -114,7 +114,7 @@
* otherwise the new scheme is used. If that fails and "use_both_schemes"
* is set, then the driver will make another attempt, using the other scheme.
*/
-static int old_scheme_first = 0;
+static int old_scheme_first = 1;
module_param(old_scheme_first, bool, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(old_scheme_first,
"start with the old device initialization scheme");
@@ -2158,6 +2158,13 @@
return retval;
}
+
+#include <asm/mach/irq.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+
+#include <asm/arch/ezx.h>
+#include <asm/arch/ezx-bp.h>
/* Reset device, (re)assign address, get device descriptor.
* Device connection must be stable, no more debouncing needed.
* Returns device in USB_STATE_ADDRESS, except on error.
@@ -2195,6 +2202,35 @@
delay = HUB_LONG_RESET_TIME;
mutex_lock(&usb_address0_mutex);
+
+
+ pxa_gpio_mode(0 | GPIO_IN);
+ if(!pxa_gpio_get_value(0))
+ {
+ printk("bp enter sleep\n");
+ unsigned long begin;
+ if(pxa_gpio_get_value(96))
+ {
+ pxa_gpio_set_value(96, 0);
+ udelay(125);
+ pxa_gpio_set_value(96, 1);
+
+ }else {
+ pxa_gpio_set_value(96, 1);
+ udelay(125);
+ pxa_gpio_set_value(96, 0);
+
+ }
+ begin = jiffies;
+ while((!pxa_gpio_get_value(0)) && (jiffies < (begin+HZ)));
+
+ if(!pxa_gpio_get_value(0))
+ {
+ printk("%s: Wakeup BP timeout! BP is still in sleep
state!\n", __FUNCTION__);
+ }
+ }else{
+ printk("bp is alive\n");
+ }
/* Reset the device; full speed may morph to high speed */
retval = hub_port_reset(hub, port1, udev, delay);
Index: linux-2.6.24.1/drivers/usb/host/ohci-pxa27x.c
===================================================================
--- linux-2.6.24.1.orig/drivers/usb/host/ohci-pxa27x.c 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/drivers/usb/host/ohci-pxa27x.c 2008-07-05
13:28:37.000000000 +0800
@@ -95,14 +95,17 @@
if (retval < 0)
return retval;
+
+
+ UHCHR = UHCHR & ~(UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
- UHCHR &= ~UHCHR_SSE;
+ //UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ //UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ //if (PSSR & PSSR_OTGPH)
+ // PSSR |= PSSR_OTGPH;
return 0;
}
Index: linux-2.6.24.1/include/asm-arm/arch-pxa/ezx-bp.h
===================================================================
--- linux-2.6.24.1.orig/include/asm-arm/arch-pxa/ezx-bp.h 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/include/asm-arm/arch-pxa/ezx-bp.h 2008-07-05
13:28:37.000000000 +0800
@@ -5,4 +5,5 @@
int gpio_wdi2;
int gpio_rdy;
int gpio_mcu_int_sw;
+ int gpio_aprdy;
};
Index: linux-2.6.24.1/include/asm-arm/arch-pxa/ezx.h
===================================================================
--- linux-2.6.24.1.orig/include/asm-arm/arch-pxa/ezx.h 2008-07-05
13:28:32.000000000 +0800
+++ linux-2.6.24.1/include/asm-arm/arch-pxa/ezx.h 2008-07-05
13:28:37.000000000 +0800
@@ -62,12 +62,12 @@
#define GPIO_SPI_MISO 26 /* PCAP SPI port SSPRXD */
/* blue tooth control PIN */
-#define GPIO_BT_WAKEUP 2 /* AP wake up bluetooth module */
-#define GPIO_BT_HOSTWAKE 14 /* bluetooth module wake up Ap module */
-#define GPIO_BT_RESET 56 /* AP reset bluetooth module */
+#define GPIO_BT_WAKEUP 57 /* AP wake up bluetooth module
*/
+#define GPIO_BT_HOSTWAKE 13 /* bluetooth module wake up Ap module */
+#define GPIO_BT_RESET 37 /* AP reset bluetooth module */
/* control LCD high - OFF low -- ON */
-#define GPIO_LCD_OFF 116 /* control LCD */
+#define GPIO_LCD_OFF 78 /* control LCD */
/* FFUART PIN */
#define GPIO_ICL_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
@@ -98,12 +98,12 @@
#define GPIO_SPI_MISO 26 /* PCAP SPI port SSPRXD */
/* blue tooth control PIN */
-#define GPIO_BT_WAKEUP 2 /* AP wake up bluetooth module */
-#define GPIO_BT_HOSTWAKE 14 /* bluetooth module wake up Ap module */
-#define GPIO_BT_RESET 56 /* AP reset bluetooth module */
+#define GPIO_BT_WAKEUP 57 /* AP wake up bluetooth module
*/
+#define GPIO_BT_HOSTWAKE 13 /* bluetooth module wake up Ap module */
+#define GPIO_BT_RESET 37 /* AP reset bluetooth module */
/* control LCD high - OFF low -- ON */
-#define GPIO_LCD_OFF 116 /* control LCD */
+#define GPIO_LCD_OFF 78 /* control LCD */
/* FFUART PIN */
#define GPIO_ICL_FFRXD_MD (53 | GPIO_ALT_FN_1_IN)
