Em Seg, 2009-05-04 às 00:20 +0300, Ilya Petrov escreveu: > 2009/5/3 Daniel Ribeiro <drw...@gmail.com>: > > Em Dom, 2009-05-03 às 22:41 +0300, Ilya Petrov escreveu: > >> 2009/5/3 Daniel Ribeiro <drw...@gmail.com>: > >> > EOC will interrupt PXA when you connect the cable. > >> > >> ok. how can i catch this? > > > > Isnt it being caught already? Last time i checked this part of the code > > it was working... > > > > Its GPIO10, set to eoc_irq(), which in turn schedules eoc_work(). > > strange. i tried this first: it doesn`t execute on every plug/unplug of cable
If ISR is not properly cleared it will not interrupt again. There are probably bugs on the code.. :) > > > > > eoc_work is currently a NOP, that just prints the interrupts from the > > ISR register. The SENSE, ISR and MSR registers use the same bits, the > > rule is: Any change on SENSE rises ISR in case MSR is low and a > > interrupt is sent to pxa. > > > > So, if you want to monitor bit 4(INT_ID), then you clear bit 4 of MSR to > > enable the irq, > > hmm. according to code _all_ bits are cleared in eoc_probe: > ret = eoc_reg_write(EOC_REG_INT_MASK, 0x0); //fef); > > maby this should be written after every event? No. But ISR bits need to be cleared after each event. Not all, but the ones that you want to monitor. > so setting MSR bit to 0 enables some event, > ISR value points which event triggered irq, > and corresponding bit in SENSE indicates current state of thing triggered > event. > > correct? Exact! And more than one event may be "delivered" by a single IRQ, so you get just a single interrupt, but N ISR bits goes 1. -- Daniel Ribeiro
