Quoting r. Roland Dreier <[EMAIL PROTECTED]>: > Subject: Re: userspace doorbells > > Michael> Roland, I see you have made the doorbell page volatile. > Michael> This makes sence, and must be enough on x86_64, but for > Michael> this to work on PPC, wont you still need to insert a > Michael> write memory barrier, to guard against the CPU > Michael> re-ordering writes to hardware and to the WQE? Since you > Michael> do it in kernel, why not in userspace? > > I'm working on it... see the <infiniband/arch.h> file I added to > libibverbs for the start of my plan. > > - R. >
OK, makes sence. I expect you'll need rmb for CQE polling and wmb for doorbells, just like we do for kernel code. Hmm, and I expect pthread_spin_lock may provide a generic barrier implementation: it seems pthread_spin_lock just has to include an rmb, pthread_spin_unlock - a wmb. -- MST - Michael S. Tsirkin _______________________________________________ openib-general mailing list openib-general@openib.org http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
