On Mon, Oct 10, 2005 at 02:26:52PM -0700, Grant Grundler wrote: ... > If it's interleaving, every other cacheline will be "local".
ISTR AMD64 was page-interleaved but then got confused by documents describing "128-bit" 2-way interleave. I now realize the 128bit is refering to interleave between two "banks" of memory behind each memory controller. ie 2 * 128-bit provides in the 32-byte cacheline size that most x86 programs expect. Anyway, I'm hoping that we'll see a consistent result if node interleave is turned off. sorry for the confusion, grant _______________________________________________ openib-general mailing list openib-general@openib.org http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general