> > Also on a related note, have you checked the driver for the needed PCI > posting flushes? > > > + > > + /* Disable IRQs by clearing the interrupt mask */ > > + writel(1, c2dev->regs + C2_IDIS); > > + writel(0, c2dev->regs + C2_NIMR0); > > like here...
This code is followed by a call to c2_reset(), which interacts with the firmware on the adapter to quiesce the hardware. So I don't think we need to wait here for the posted writes to flush... > > + > > + elem = tx_ring->to_use; > > + elem->skb = skb; > > + elem->mapaddr = mapaddr; > > + elem->maplen = maplen; > > + > > + /* Tell HW to xmit */ > > + __raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR); > > + __raw_writew(cpu_to_be16(maplen), elem->hw_desc + C2_TXP_LEN); > > + __raw_writew(cpu_to_be16(TXP_HTXD_READY), elem->hw_desc + C2_TXP_FLAGS); > > or here > No need here. This logic submits the packet for transmission. We don't assume it is transmitted until we (after a completion interrupt usually) read back the HTXD entry and see the TXP_HTXD_DONE bit set (see c2_tx_interrupt()). Steve. _______________________________________________ openib-general mailing list openib-general@openib.org http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
