On Tue, Oct 31, 2006 at 03:34:47PM -0500, Richard B. Johnson wrote: > If you write to the PCI bus and then you read the result, the read > __might__ be the > read that flushes any posted writes rather than the read of device
Config space writes aren't posted, they're delayed. So, for example, you can do the config write on the primary bus, then it hits a bridge on its way to the destination device. The bridge is entitled (obviously, it's unlikely to) drop it, and then the config read can pass by the config write. I'm beginning to think Michael Tsirkin has the only solution to this -- architectures need to check that their hardware blocks until the config write completion has occurred (and if not, simulate that it has in software). _______________________________________________ openib-general mailing list openib-general@openib.org http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
