Thanks for the reply. I finally noticed that the integrated memory controller on sandy/ivy bridge have an integrated smbus function:
https://lkml.org/lkml/2013/12/20/525 I’m looking at that as well. A. On 24 Mar 2014, at 19:20, Corey Minyard <[email protected]> wrote: > Looking over this, I really don't know. You should be able to do it with > the right commands, but it would take some work. > > -corey > > On 03/20/2014 02:24 PM, Alun Evans wrote: >> Using an i2c sniffer (http://www.totalphase.com/products/aardvark-i2cspi/), >> I built a custom harness with a DIMM riser and hooked it up to the >> SDA/SCL/GND pins on an LRDIMM I had in the chassis, then I did the following: >> >> 1) booted the system. >> 2) Ran `stress` tool to heat up the memory. >> 3) Ran super micro’s ipmicfg query. >> 4) Ran my OpenIPMI scanning program (attached). >> >>> $ stress -m 8 >>> stress: info: [2278] dispatching hogs: 0 cpu, 0 io, 8 vm, 0 hdd >>> >>> $ sudo ./ipmicfg -nm cpumemtemp >>> CPU#0 = 30(c) >>> CPU#1 = 34(c) >>> [CPU#0]CHANNEL#0, DIMM#0(P1_DIMMA1) = 24(c) >>> [CPU#1]CHANNEL#0, DIMM#0(P2_DIMME1) = 26(c) >>> $ sudo ./ipmicfg -nm cpumemtemp >>> CPU#0 = 35(c) >>> CPU#1 = 38(c) >>> [CPU#0]CHANNEL#0, DIMM#0(P1_DIMMA1) = 25(c) >>> [CPU#1]CHANNEL#0, DIMM#0(P2_DIMME1) = 27(c) >>> <snip> >>> $ sudo ./ipmicfg -nm cpumemtemp >>> CPU#0 = 38(c) >>> CPU#1 = 40(c) >>> [CPU#0]CHANNEL#0, DIMM#0(P1_DIMMA1) = 30(c) >>> [CPU#1]CHANNEL#0, DIMM#0(P2_DIMME1) = 32(c) >> >> Remembering this i2c Addressing Summary: >> >> WP=Write Protection >> >> +----------------+--------------+----------+----+------+ >> | Memory Area | Device Type | Chip En | RW | Hex | >> | Function | [b7 b6 b5 b4]|[b3 b2 b1]|[b0]| Base | >> +----------------+--------------+----------+----+------+ >> | R/W Temp Reg | 0 0 1 1 | A2 A1 A0 | RW | 0x18 | >> +----------------+--------------+----------+----+------+ >> | Set-WP | | 0 0 1 | 0 | | >> | Clear-WP | | 0 1 1 | 0 | | >> | PermSet-WP | 0 1 1 0 | A2 A1 A0 | 0 | 0x30 | >> | Read-SWP | | 0 0 1 | 1 | | >> | Read-PSWP | | A2 A1 A0 | 1 | | >> +----------------+--------------+----------+----+------+ >> | Repeat Mem Buf | 1 0 1 1 | A2 A1 A0 | RW | 0x40 | >> +----------------+--------------+----------+----+------+ >> | R/W SPD memory | 1 0 1 0 | A2 A1 A0 | RW | 0x50 | >> +----------------+--------------+----------+----+------+ >> | Mem Buffer | 1 0 1 1 | A2 A1 A0 | RW | 0x58 | >> +----------------+--------------+----------+----+------+ >> >> What I noticed in the i2c-sniff.log (attached) were the following >> transactions: >> >> 1) Partial read of 0x50 -> 0x57 (twice) >> 2) Entire read of SPD at 0x50 (where there is one LRDIMM Installed) >> 3) Training via 0x58 >> 4) Polling of temp 0x18 >> >> i.e. it seems that something is continuously polling the i2c bus for the >> temperature, which I presume is the BMC. >> >> I then ran a program I’ve written `ipmi-i2c-scan.c` (attached), in the hope >> that I could scan out on that i2c bus, and see those transactions. Alas no. >> all I saw were the continued poll of the 0x18 temp register. >> >> I’ve attached the output of the program (i2c-scan.log), I did seem to read >> some data but certainly not at addresses I expected, nor data I know. >> >> I’m not sure what to make of this all, I was really hoping to gain access to >> the memory buffer @ 0x58, and that would have to be via that BMC chip on >> this system as far as I can tell. >> >> Any pointers gratefully received. >> >> >> >> A. >> > -- Alun Evans http://badgerous.net/
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