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--------------1.5.3.1
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Adjust DCLK ratio to match the desired pixclock.

Signed-off-by: Chia-I Wu <[EMAIL PROTECTED]>
---
 drivers/video/glamo/glamo-core.c |  105 +++++++++++++++++++++++++++----------
 drivers/video/glamo/glamo-core.h |    2 +
 drivers/video/glamo/glamo-fb.c   |    5 ++
 3 files changed, 83 insertions(+), 29 deletions(-)
--------------1.5.3.1
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diff --git a/drivers/video/glamo/glamo-core.c b/drivers/video/glamo/glamo-core.c
index 3a53e00..e2c2b95 100644
--- a/drivers/video/glamo/glamo-core.c
+++ b/drivers/video/glamo/glamo-core.c
@@ -488,9 +488,85 @@ void glamo_engine_reset(struct glamo_core *glamo, enum 
glamo_engine engine)
        spin_lock(&glamo->lock);
        __reg_clear_bit(glamo, rst->reg, rst->val);
        spin_unlock(&glamo->lock);
+
+       msleep(1);
 }
 EXPORT_SYMBOL_GPL(glamo_engine_reset);
 
+enum glamo_pll {
+       GLAMO_PLL1,
+       GLAMO_PLL2,
+};
+
+static int glamo_pll_rate(struct glamo_core *glamo,
+                         enum glamo_pll pll)
+{
+       u_int16_t reg;
+       unsigned int div = 512;
+       /* FIXME: move osci into platform_data */
+       unsigned int osci = 32768;
+
+       if (osci == 32768)
+               div = 1;
+
+       switch (pll) {
+       case GLAMO_PLL1:
+               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
+               break;
+       case GLAMO_PLL2:
+               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
+               break;
+       default:
+               return -EINVAL;
+       }
+       return (osci/div)*reg;
+}
+
+int glamo_engine_reclock(struct glamo_core *glamo,
+                        enum glamo_engine engine,
+                        int ps)
+{
+       int pll, khz;
+       u_int16_t reg, mask, val = 0;
+
+       if (!ps)
+               return 0;
+
+       switch (engine) {
+       case GLAMO_ENGINE_LCD:
+               pll = GLAMO_PLL1;
+               reg = GLAMO_REG_CLOCK_GEN7;
+               mask = 0xff;
+               break;
+       default:
+               dev_warn(&glamo->pdev->dev,
+                        "reclock of engine 0x%x not supported\n", engine);
+               return -EINVAL;
+               break;
+       }
+
+       pll = glamo_pll_rate(glamo, pll);
+       khz = 1000000000UL / ps;
+
+       if (khz)
+               val = (pll / khz) / 1000;
+
+       dev_dbg(&glamo->pdev->dev,
+                       "PLL %d, kHZ %d, div %d\n", pll, khz, val);
+
+       if (val) {
+               val--;
+
+               reg_set_bit_mask(glamo, reg, mask, val);
+               msleep(5); /* wait some time to stabilize */
+
+               return 0;
+       } else {
+               return -EINVAL;
+       }
+}
+EXPORT_SYMBOL_GPL(glamo_engine_reclock);
+
 /***********************************************************************
  * script support
  ***********************************************************************/
@@ -643,35 +719,6 @@ static const struct glamo_script regs_vram_8mb = {
 };
 #endif
 
-enum glamo_pll {
-       GLAMO_PLL1,
-       GLAMO_PLL2,
-};
-
-static int glamo_pll_rate(struct glamo_core *glamo,
-                                  enum glamo_pll pll)
-{
-       u_int16_t reg;
-       unsigned int div = 512;
-       /* FIXME: move osci into platform_data */
-       unsigned int osci = 32768;
-
-       if (osci == 32768)
-               div = 1;
-
-       switch (pll) {
-       case GLAMO_PLL1:
-               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
-               break;
-       case GLAMO_PLL2:
-               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
-               break;
-       default:
-               return -EINVAL;
-       }
-       return (osci/div)*reg;
-}
-
 enum glamo_power {
        GLAMO_POWER_ON,
        GLAMO_POWER_STANDBY,
diff --git a/drivers/video/glamo/glamo-core.h b/drivers/video/glamo/glamo-core.h
index a66e847..215bd9e 100644
--- a/drivers/video/glamo/glamo-core.h
+++ b/drivers/video/glamo/glamo-core.h
@@ -47,5 +47,7 @@ enum glamo_engine {
 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
+int glamo_engine_reclock(struct glamo_core *glamo,
+                        enum glamo_engine engine, int ps);
 
 #endif /* __GLAMO_CORE_H */
diff --git a/drivers/video/glamo/glamo-fb.c b/drivers/video/glamo/glamo-fb.c
index 2a5814f..8ccf9fc 100644
--- a/drivers/video/glamo/glamo-fb.c
+++ b/drivers/video/glamo/glamo-fb.c
@@ -201,6 +201,11 @@ static void glamofb_activate_var(struct glamofb_handle 
*glamo,
 
        glamofb_cmd_mode(glamo, 1);
 
+       if (var->pixclock)
+               glamo_engine_reclock(glamo->mach_info->glamo,
+                                    GLAMO_ENGINE_LCD,
+                                    var->pixclock);
+
        /* XXX highest bits of the following two regs have other meanings */
        reg_write(glamo, GLAMO_REG_LCD_WIDTH, var->xres);
        reg_write(glamo, GLAMO_REG_LCD_HEIGHT, var->yres);

--------------1.5.3.1--



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