Hey Andy, hey Werner!! thanks a lot for these information. I already assumed that there are some higher level mechanism. Anyway it's good to know, at which base clock the AHB and APB components are running. Maybe SDRAM get's unstable at 133MHz because of the external chip attached.... and of course it's the upper limit of the MSP. Seems that there are also no other values one could try (e.g. 120MHz) without changing FCLK.
As long as all the peripherals on the AHB (NAND-controller, NOR, GLAMO, ...) are setup by waitstates this would also require to look into tons of timing diagrams and testing. Nevertheless, i'm really interested in this part of code, especially the steppingstone mechanism. So i should digg a bit deeper through the bootloader code, to get better understanding. Best regards, scholbert -- View this message in context: http://n2.nabble.com/PLL---clock-settings-on-GTA02%3A-u-boot-vs.-qi-tp2274434p2275322.html Sent from the Openmoko Kernel mailing list archive at Nabble.com.
