Some of the rate selection logic in s3c64xx_setrate_clksrc uses what appears to be parent clock selection logic. This patch corrects it.
I also added a check for overly large dividers to prevent them from changing unrelated clocks. Signed-off-by: Werner Almesberger <[email protected]> --- Index: cam/arch/arm/plat-s3c64xx/s3c6400-clock.c =================================================================== --- cam.orig/arch/arm/plat-s3c64xx/s3c6400-clock.c 2009-02-27 18:55:24.000000000 +0800 +++ cam/arch/arm/plat-s3c64xx/s3c6400-clock.c 2009-02-27 18:56:07.000000000 +0800 @@ -239,10 +239,12 @@ rate = clk_round_rate(clk, rate); div = clk_get_rate(clk->parent) / rate; + if (div > 16) + return -EINVAL; val = __raw_readl(reg); - val &= ~sclk->mask; - val |= (rate - 1) << sclk->shift; + val &= ~(0xf << sclk->shift); + val |= (div - 1) << sclk->shift; __raw_writel(val, reg); return 0;
