Yes, the USB is the critical bottleneck not only for SWD but also JTAg
which I had occasion to check in practice recently. Please note that LibSWD
can easily become a part of the smart adapter firmware if necessary (it
would be nice to check its functionalities firsr however).
It would be nice to have adapter that would include whole openocd distribu
>
> On Fri, May 18, 2012 at 5:38 PM, simonqian.openocd
> <[email protected]> wrote:
> > Here is my test under Win7-64bit by msys.
> >
> > 1125KHz JTAG:
> > stm32x mass erase complete
> > wrote 6592 bytes from file Versaloon.hex in 0.345020s (18.658 KiB/s)
> > verified 6592 bytes in 0.082004s (78.502 KiB/s)
> > dumped 131072 bytes in 2.292131s (55.843 KiB/s)
> > verified 131072 bytes in 0.323019s (396.262 KiB/s)
> > stm32x mass erase complete
> > Warn : no flash bank found for address 8010000
> > wrote 65536 bytes from file test.bin in 1.958112s (32.685 KiB/s)
> > verified 131072 bytes in 0.326019s (392.615 KiB/s)
> > 20480 bytes written at address 0x20000000
> > downloaded 20480 bytes in 0.360021s (55.552 KiB/s)
> >
> > 2250KHz JTAG:
> > stm32x mass erase complete
> > wrote 6592 bytes from file Versaloon.hex in 0.301017s (21.386 KiB/s)
> > verified 6592 bytes in 0.073005s (88.179 KiB/s)
> > dumped 131072 bytes in 1.543088s (82.951 KiB/s)
> > verified 131072 bytes in 0.313018s (408.922 KiB/s)
> > stm32x mass erase complete
> > Warn : no flash bank found for address 8010000
> > wrote 65536 bytes from file test.bin in 1.903109s (33.629 KiB/s)
> > verified 131072 bytes in 0.317018s (403.763 KiB/s)
> > 20480 bytes written at address 0x20000000
> > downloaded 20480 bytes in 0.241014s (82.983 KiB/s)
> >
> > 4500KHz JTAG:
> > stm32x mass erase complete
> > wrote 6592 bytes from file Versaloon.hex in 0.278016s (23.155 KiB/s)
> > verified 6592 bytes in 0.075004s (85.829 KiB/s)
> > dumped 131072 bytes in 1.163066s (110.054 KiB/s)
> > verified 131072 bytes in 0.309018s (414.215 KiB/s)
> > stm32x mass erase complete
> > Warn : no flash bank found for address 8010000
> > wrote 65536 bytes from file test.bin in 1.874107s (34.150 KiB/s)
> > verified 131072 bytes in 0.310018s (412.879 KiB/s)
> > 20480 bytes written at address 0x20000000
> > downloaded 20480 bytes in 0.187011s (106.946 KiB/s)
> >
> > 9000KHz JTAG:
> > stm32x mass erase complete
> > wrote 6592 bytes from file Versaloon.hex in 0.264015s (24.383 KiB/s)
> > verified 6592 bytes in 0.068004s (94.664 KiB/s)
> > dumped 131072 bytes in 0.979056s (130.738 KiB/s)
> > verified 131072 bytes in 0.305017s (419.649 KiB/s)
> > stm32x mass erase complete
> > Warn : no flash bank found for address 8010000
> > wrote 65536 bytes from file test.bin in 1.862107s (34.370 KiB/s)
> > verified 131072 bytes in 0.315018s (406.326 KiB/s)
> > 20480 bytes written at address 0x20000000
> > downloaded 20480 bytes in 0.153009s (130.711 KiB/s)
> >
> > 18000KHz+ JTAG:
> > Fail
> >
> > SWD:
> > stm32x mass erase complete
> > wrote 6592 bytes from file Versaloon.hex in 0.296016s (21.747 KiB/s)
> > verified 6592 bytes in 0.069004s (93.292 KiB/s)
> > dumped 131072 bytes in 1.915110s (66.837 KiB/s)
> > verified 131072 bytes in 0.313018s (408.922 KiB/s)
> > stm32x mass erase complete
> > Warn : no flash bank found for address 8010000
> > wrote 65536 bytes from file test.bin in 1.901109s (33.665 KiB/s)
> > verified 131072 bytes in 0.313018s (408.922 KiB/s)
> > 20480 bytes written at address 0x20000000
> > downloaded 20480 bytes in 0.255015s (78.427 KiB/s)
> >
> > The result is interesting, the memory rw using Versaloon is even not much
> > slow than JTAGKey2 which is 480MHz USB.
>
> One thing that Versaloon and other MCU based HW
> has advantage is that the MCU does quite some time
> critical work. On the contrary, FTDI based HW will be
> at the mercy of the host since there are no intelligence
> within the HW.
> http://openocd.sourceforge.net/doc/doxygen/html/ft2232_8c.html
> +++++
> FT2232 based JTAG adapters are "dumb" not "smart", because
> most JTAG request/response interactions involve round trips
> over the USB link. A "smart" JTAG adapter has intelligence
> close to the scan chain, so it can for example poll quickly for a
> status change (usually taking on the order of microseconds not
> milliseconds) before beginning a queued transaction which
> require the previous one to have completed.
> +++++
>
> > So this means the USB delay is not vital for ADIv5.
>
> See the above, the USB delay does play a big part to
> reduce the high speed USB advantage of FTx232H (125us
> USB microframe time).
>
> A better solution for FTx232H will be to add an MCU
> (or CPLD or FPGA).
>
> Another possibility is for the MCU based HW to use
> high speed capable USB MCU.
>
> > And the speed of SWD is almost the same as 2000KHz JTAG.
>
> Interesting results.
>
> --
> Xiaofan
>
>
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