This is an automated email from Gerrit. Tomasz CEDRO ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1046
-- gerrit commit ff2cd8141dc577cf066324b04964eedc8b546384 Author: Tomek CEDRO <[email protected]> Date: Thu Nov 29 23:52:14 2012 +0100 Added example configuration tcl/target/lpc17xx-swd.cfg and tcl/target/lpc1768-swd.cfg for testing LibSWD+OpenOCD with LPC17xx devices using SWD transport. Please ask Akos Vandra for support on this configuration :-) Change-Id: Ie40f1182974772dde2adc424abd9d60db1d63df6 Signed-off-by: Tomek CEDRO <[email protected]> diff --git a/tcl/target/lpc1768-swd.cfg b/tcl/target/lpc1768-swd.cfg new file mode 100644 index 0000000..385ed8a --- /dev/null +++ b/tcl/target/lpc1768-swd.cfg @@ -0,0 +1,17 @@ +# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1768 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx-swd.cfg]; diff --git a/tcl/target/lpc17xx-swd.cfg b/tcl/target/lpc17xx-swd.cfg new file mode 100644 index 0000000..80b284a --- /dev/null +++ b/tcl/target/lpc17xx-swd.cfg @@ -0,0 +1,100 @@ +# Main file for NXP LPC17xx Cortex-M3 +# +# !!!!!! +# +# This file should not be included directly, rather +# by the lpc1751.cfg, lpc1752.cfg, etc. which set the +# needed variables to the appropriate values. +# +# !!!!!! +# +# SWD helper configuration to test OpenOCD + LibSWD based on JTAG configuration. +# Please ask Akos Vandra on the mailing list for details :-) +# + +# LPC17xx chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." +} + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + set _CCLK 4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." +} + +#delays on reset lines +adapter_nsrst_delay 200 + +#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +swd newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME + +# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +adapter_khz 10 + +$_TARGETNAME configure -event reset-init { + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + mww 0x400FC040 0x01 +} + +# if srst is not fitted use VECTRESET to +# perform a soft reset - SYSRESETREQ is not supported +cortex_m3 reset_config vectreset -- ------------------------------------------------------------------------------ LogMeIn Rescue: Anywhere, Anytime Remote support for IT. Free Trial Remotely access PCs and mobile devices and provide instant support Improve your efficiency, and focus on delivering more value-add services Discover what IT Professionals Know. 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