Thanks Spencer,
I have made some local changes to add a simple handler for a " cortex_a8
maskisr [ 'on' | 'off' ] " command. It seems to do what I want it to do.
I've attached the diff if you are interested in commenting. Who knows, I
could be inadvertently ruining something.
I am using: Open On-Chip Debugger 0.7.0-dev-00079-g08ddb19
(2013-02-14-19:27).
Thanks again,
Ken
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index e1c4c9c..2b2558d 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2431,6 +2431,81 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
return cortex_a8_init_debug_access(target);
}
+
+COMMAND_HANDLER(cortex_a8_handle_mask_interrupts_command)
+{+ struct
target *target = get_current_target(CMD_CTX);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
+ uint32_t dscr;
+ int retval;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("%s: target not halted", __func__);
+ return ERROR_TARGET_INVALID;
+ }
+
+ if (CMD_ARGC == 0) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base +
CPUDBG_DSCR,
&dscr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read DSCR register");
+ return retval;
+ }
+
+ if (dscr & DSCR_INT_DIS )
+ LOG_INFO("ON");
+ else {
+ LOG_INFO("OFF");
+ }
+ return ERROR_OK;
+ }
+
+ if (strncmp(CMD_ARGV[0], "on", 3) == 0) {
+
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base +
CPUDBG_DSCR,
&dscr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read DSCR register");
+ return retval;
+ }
+
+ if (!(dscr & DSCR_INT_DIS)) {
+ retval = mem_ap_sel_write_atomic_u32(swjdp,
swjdp_debugap,
+ armv7a->debug_base
+ CPUDBG_DSCR,
dscr | DSCR_INT_DIS);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not write DSCR register");
+ return retval;
+ }
+ }
+
+ } else if (strncmp(CMD_ARGV[0], "off", 4) == 0) {
+
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base +
CPUDBG_DSCR,
&dscr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read DSCR register");
+ return retval;
+ }
+ LOG_DEBUG("dscr: %8.8" PRIx32, dscr);
+
+ if (dscr & DSCR_INT_DIS) {
+ retval = mem_ap_sel_write_atomic_u32(swjdp,
swjdp_debugap,
+ armv7a->debug_base
+ CPUDBG_DSCR,
dscr & ~DSCR_INT_DIS);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not write DSCR register");
+ return retval;
+ }
+ }
+
+ } else {
+ LOG_DEBUG("Invalid maskisr command %s", CMD_ARGV[0]);
+ return ERROR_FAIL;
+ }
+
+ return retval;
+}
+
COMMAND_HANDLER(cortex_a8_handle_smp_off_command)
{
struct target *target = get_current_target(CMD_CTX);
@@ -2523,6 +2598,13 @@ static const struct command_registration
cortex_a8_exec_command_handlers[] = {
.help = "display/fix current core played to gdb",
.usage = "",
},
+ {
+ .name = "maskisr",
+ .handler = cortex_a8_handle_mask_interrupts_command,
+ .mode = COMMAND_EXEC,
+ .help = "mask cortex_a8 interrupts",
+ .usage = "['on'|'off']",
+ },
COMMAND_REGISTRATION_DONE
-----Original Message-----
From: Spencer Oliver [mailto:[email protected]]
Sent: Friday, March 01, 2013 3:00 AM
To: Kenneth Lee
Cc: OpenOCD Devel
Subject: Re: [OpenOCD-devel] cortex a8 maskisr during GDB stepping
On 28 February 2013 19:37, Kenneth Lee <[email protected]> wrote:
> I am trying to use OpenOCD with GDB to debug C code running on a Cortex
> A8
> (AM335x). One of the issues I am running into is the MCU jumping to the
> ISR vector every time I try to step using GDB, which results in
> stepping to the ISR vector rather than the next line of code in the
> current source file.
>
> If I do a “mon reg cpsr 0x1d3” from the gdb command
> line to disable IRQ’a , then the stepping works. Obviously, this is
> not the correct way to do this.
>
> So the general question is, is there a way I can step through code
> without gdb jumping to the ISR vector?
>
either what you do above or as a workaround use tbreak + cont.
>
>
> An alternate question, and maybe be related is: Does the OpenOCD
> cortex A8 module have anything like the M3 maskisr functionality that
> I can hook into GDB?
>
support would need adding i am afraid.
I am not that familiar with the cortex-a8 (no hardware) but the register to
use seems to be CPUDBG_DSCR, bit DSCR_INT_DIS.
Cheers
Spen
openocd_cortexa8_maskisr.diff
Description: Binary data
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