I am trying to make some initial changes to make a A15 board work.
(gdb) mon dap info 0
AP ID register 0x44770001
Type is MEM-AP AHB
AP BASE 0xffffffff
No ROM table present
(gdb) mon dap info 1
AP ID register 0x24770002
Type is MEM-AP APB
AP BASE 0x80000000
ROM table in legacy format
MEMTYPE System memory not present. Dedicated debug bus.
ROMTABLE[0x0] = 0x100003
Component base address 0x80100000,start address 0x80100000
Component class is 0x1, ROM table
Peripheral ID[4..0] = hex 04 00 3b b4 af
Part is Cortex-A15 Debug (Debug Unit)
ROMTABLE[0x4] = 0x200003
Component base address 0x80200000,start address 0x80200000
Component class is 0x9, CoreSight component
Type is 0x12, Trace Link, Funnel, router
Peripheral ID[4..0] = hex 04 00 2b b9 08
Part is Coresight CSTF (Trace Funnel)
ROMTABLE[0x8] = 0x400003
Component base address 0x80400000,start address 0x80400000
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
Peripheral ID[4..0] = hex 04 00 4b b9 12
Part is Coresight TPIU (Trace Port Interface Unit)
ROMTABLE[0xc] = 0x0
End of ROM table
using dap apsel 1 in teh script as recommended by ARM. Which means I
am using the MEM-AP APB
However is it possible to read memory and step into code when MMU is
disabled. I am having a situation where I need to debug code at a
point where va=pa, however OpenOcd needs the MMU to be enabled. Is
there any way to read when MMU is disabled.
Also I am planning to commit the initial code for review as well.
However I need a way to distinguish between A15 and A9 in the armv7a.c
to make sense of the ttbr0/1 registers. Can anyone recommend a good
way to add that in this part of the code.
I am pasting the code snippet
openocd/src/target/armv7a.c
static int armv7a_read_ttbcr(struct target *target)
{
..
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 0),
+ &ttbr0);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 1),
+ &ttbr1);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_INFO("ttbcr %x ttbr0 %x ttbr1 %x", ttbcr, ttbr0, ttbr1);
+
armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
- armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
-#if 0
- LOG_INFO("ttb1 %s ,ttb0_mask %x",
- armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
- armv7a->armv7a_mmu.ttbr0_mask);
-#endif
- if (armv7a->armv7a_mmu.ttbr1_used == 1) {
+ armv7a->armv7a_mmu.ttbr0_used = ((ttbcr & 0x7) == 0) ? 1 : 0;
+
+ /* Fix this for cortex a8 a9
+ armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
+ */
+
+ /*
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * document # ARM DDI 0406C
+ */
+ armv7a->armv7a_mmu.ttbr0_mask = 1 << (14 - ((ttbcr & 0x7)));
+
+ LOG_DEBUG("ttb0 %s ttb1 %s, ttb0_mask %x",
+ armv7a->armv7a_mmu.ttbr0_used ? "used" : "not used",
+ armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
+ armv7a->armv7a_mmu.ttbr0_mask);
+
+ if (armv7a->armv7a_mmu.ttbr0_used == 1) {
+ LOG_INFO("SVC access above %x",
+ (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
+ armv7a->armv7a_mmu.os_border = 0xffffffff &
armv7a->armv7a_mmu.ttbr0_mask;
+ } else if (armv7a->armv7a_mmu.ttbr1_used == 1) {
LOG_INFO("SVC access above %x",
(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
armv7a->armv7a_mmu.os_border = 0xffffffff &
armv7a->armv7a_mmu.ttbr0_mask;
Thanks in advance.
Kamal
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