This is an automated email from Gerrit. Sergio Chico ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1806
-- gerrit commit 9ffc706e53490ef3e2a59882927b3dc46b991c85 Author: Sergio Chico <[email protected]> Date: Sun Nov 10 16:03:40 2013 +0100 topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc This add support to the Xilinx BSCAN_* virtual JTAG interface. This is the Xilinx equivalent of the Altera sld_virtual_jtag interface, it allows a user to connect to the debug unit through the main FPGA JTAG connection. Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188 Signed-off-by: Sergio Chico <[email protected]> diff --git a/doc/openocd.texi b/doc/openocd.texi index aa0bb5d..5f2b89e 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4181,10 +4181,11 @@ There are several variants defined: @item @code{pxa3xx} ... instruction register length is 11 bits @end itemize @item @code{openrisc} -- this is an OpenRISC 1000 core. -The current implementation supports two JTAG TAP cores: +The current implementation supports three JTAG TAP cores: @itemize @minus @item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag}) @item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) +@item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf}) @end itemize And two debug interfaces cores: @itemize @minus @@ -7517,8 +7518,8 @@ The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be configured with any of the TAP / Debug Unit available. @subsection TAP and Debug Unit selection commands -@deffn Command {tap_select} (@option{vjtag}|@option{mohor}) -Select between the Altera Virtual JTAG and Mohor TAP. +@deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan}) +Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP. @end deffn @deffn Command {du_select} (@option{adv}|@option{mohor}) [option] Select between the Advanced Debug Interface and the classic one. diff --git a/src/target/openrisc/Makefile.am b/src/target/openrisc/Makefile.am index 61e4742..f1e7eaa 100644 --- a/src/target/openrisc/Makefile.am +++ b/src/target/openrisc/Makefile.am @@ -7,7 +7,8 @@ OPENRISC_SRC = \ or1k.c \ or1k_du_adv.c \ or1k_tap_mohor.c \ - or1k_tap_vjtag.c + or1k_tap_vjtag.c \ + or1k_tap_xilinx_bscan.c noinst_HEADERS = \ or1k.h \ diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c index 8d8ad40..8d65d46 100644 --- a/src/target/openrisc/or1k.c +++ b/src/target/openrisc/or1k.c @@ -1179,6 +1179,7 @@ static int or1k_target_create(struct target *target, Jim_Interp *interp) or1k_create_reg_list(target); or1k_tap_vjtag_register(); + or1k_tap_xilinx_bscan_register(); or1k_tap_mohor_register(); or1k_du_adv_register(); diff --git a/src/target/openrisc/or1k_tap.h b/src/target/openrisc/or1k_tap.h index 64bdef2..4314822 100644 --- a/src/target/openrisc/or1k_tap.h +++ b/src/target/openrisc/or1k_tap.h @@ -29,6 +29,7 @@ #include "or1k.h" int or1k_tap_vjtag_register(void); +int or1k_tap_xilinx_bscan_register(void); int or1k_tap_mohor_register(void); /* Linear list over all available or1k taps */ diff --git a/src/target/openrisc/or1k_tap_xilinx_bscan.c b/src/target/openrisc/or1k_tap_xilinx_bscan.c new file mode 100644 index 0000000..43f2756 --- /dev/null +++ b/src/target/openrisc/or1k_tap_xilinx_bscan.c @@ -0,0 +1,65 @@ +/*************************************************************************** + * Copyright (C) 2013 by Sergio Chico * + * [email protected] * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "or1k_tap.h" +#include "or1k.h" + +#include <jtag/jtag.h> + +#define OR1K_XILINX_TAP_INST_USER1 0x02 + +static int or1k_tap_xilinx_bscan_init(struct or1k_jtag *jtag_info) +{ + LOG_DEBUG("Initialising Xilinx Internal JTAG TAP"); + + /* Put TAP into state where it can talk to the debug interface + * by shifting in correct value to IR. + */ + + /* Ensure TAP is reset - maybe not necessary*/ + jtag_add_tlr(); + + struct jtag_tap *tap = jtag_info->tap; + struct scan_field field; + uint8_t ir_value = OR1K_XILINX_TAP_INST_USER1; + + field.num_bits = tap->ir_length; + field.out_value = &ir_value; + field.in_value = NULL; + + jtag_add_ir_scan(tap, &field, TAP_IDLE); + + return jtag_execute_queue(); +} + +static struct or1k_tap_ip xilinx_bscan_tap = { + .name = "xilinx_bscan", + .init = or1k_tap_xilinx_bscan_init, +}; + +int or1k_tap_xilinx_bscan_register(void) +{ + list_add_tail(&xilinx_bscan_tap.list, &tap_list); + return 0; +} diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg index 9daa7ab..062506e 100644 --- a/tcl/board/or1k_generic.cfg +++ b/tcl/board/or1k_generic.cfg @@ -1,6 +1,9 @@ -# If you want to use the VJTAG TAP, you must set your FPGA TAP ID here +# If you want to use the VJTAG TAP or the XILINX BSCAN, +# you must set your FPGA TAP ID here + set FPGATAPID 0x020b30dd -# Choose your TAP core (VJTAG or MOHOR) + +# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN) set TAP_TYPE VJTAG # Set your chip name set CHIPNAME or1200 @@ -39,4 +42,4 @@ foreach name [target names] { set c_blue "\033\[01;34m" set c_reset "\033\[0m" -puts [format "%sTarget ready...%s" $c_blue $c_reset] +puts [format "%sTarget ready...%s" $c_blue $c_reset] \ No newline at end of file diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index 84514ef..ee2629c 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -29,6 +29,23 @@ if { [string compare $_TAP_TYPE "VJTAG"] == 0 } { # Select the TAP core we are using tap_select vjtag + +} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } { + + if { [info exists FPGATAPID] } { + set _FPGATAPID $FPGATAPID + } else { + puts "You need to set your FPGA JTAG ID" + shutdown + } + + jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME + + # Select the TAP core we are using + tap_select xilinx_bscan } else { # OpenCores Mohor JTAG TAP ID set _CPUTAPID 0x14951185 @@ -50,4 +67,4 @@ proc ADBG_USE_HISPEED {} { return 1 } # on burst reads and writes to improve download speeds. # This option must match the RTL configured option. -du_select adv [ADBG_USE_HISPEED] +du_select adv [ADBG_USE_HISPEED] \ No newline at end of file -- ------------------------------------------------------------------------------ November Webinars for C, C++, Fortran Developers Accelerate application performance with scalable programming models. Explore techniques for threading, error checking, porting, and tuning. Get the most from the latest Intel processors and coprocessors. See abstracts and register http://pubads.g.doubleclick.net/gampad/clk?id=60136231&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
