This is an automated email from Gerrit. Uwe Bonnes ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2942
-- gerrit commit 150d36a3cf1e85d5687bea26d682869cbe12853e Author: Uwe Bonnes <[email protected]> Date: Sun Aug 23 15:04:31 2015 +0200 stm32l4: Add cpu and stlink2_1 connected board configuration. Change-Id: I20d3fcee04516eb3b9bb22933e7e366eed0c0b2e Signed-off-by: Uwe Bonnes <[email protected]> diff --git a/tcl/board/stm32l4_stlinkv21.cfg b/tcl/board/stm32l4_stlinkv21.cfg new file mode 100644 index 0000000..215d223 --- /dev/null +++ b/tcl/board/stm32l4_stlinkv21.cfg @@ -0,0 +1,14 @@ +# This is for STM32L4 boards that are connected via stlink-v2-1. +# Known boards at the moment: +# 32L476GDISCOVERY +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261635 +# NUCLEO-L476 +# (no STM docu as of 20150823) + +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32l4x.cfg] + +reset_config srst_only diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg new file mode 100644 index 0000000..677837c --- /dev/null +++ b/tcl/target/stm32l4x.cfg @@ -0,0 +1,96 @@ +# script for stm32l4x family + +# +# stm32l4 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l4x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0351 + # Section 44.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0351 + # Section 38.6.2 + # STM32L4X6 + set _BSTAPID1 0x06415041 +} + +if {[using_jtag]} { + swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter_khz 1800 + +adapter_nsrst_delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP + mww 0xE0042008 0x00001800 +} + +$_TARGETNAME configure -event trace-config { + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
