> When loading the fw.elf binary composed with the bootloader image (generated
> as described above), the bootloader section in fw.elf (.bootldr) appears to
> be filled with zeros rather than actual data. As a result, when the processor
> resets, it reads the second element of the interrupt vector (0, in this
> case), and sets pc=0, xPSR=0. This is why after a reset I would observe
> failures would begin to happen (as a reset would trigger loading 0 into xPSR).
>
> Failures only occured every-other time because erasing the flash (which
> happened without running a target algorithm on the device) causes the
> interrupt vector to contain (instead) 0xffffffff, resulting in pc=0xfffffffe,
> xPSR.T=1 on the next reset. This likely means that a reset between erase and
> writing would have also worked around the issue.
This makes sense!
After a "reset halt" the PC is loaded from the reser vector and the thumb mode
is set from the LSB of the reset vector.
In OpenOCD there is nothing that forces thumb mode before executing an
algorithm (and every angorithm for ARM in contrib/loaders/ is written in thumb).
I have not tested your patch, but the functionality seams correct.
But now that you have clear the root cause, I suggest you to update both commit
message and comment in your patch.
---
** [tickets:#203] programming st_nucleo_f7 (stm32f767) bank 2 consistently
fails**
**Status:** new
**Milestone:** 0.9.0
**Created:** Mon Aug 20, 2018 09:55 PM UTC by Cody Schafer
**Last Updated:** Wed Aug 29, 2018 07:24 PM UTC
**Owner:** nobody
In the `stm32f767zi` (on the nucleo-f767zi board), there is 2MiB of flash. When
it is configured into dual bank mode (`stm32f2x options_write 0 0xDFC 0x0080
0x0040`, presuming all other options are left at their defaults), using the
`program` command to program the second bank (`bank1_start=0x0810_0000`,
`bank2_start=0x0800_0000`) with the command `flash write_image fw.elf erase
0x100000`, the execution consistently fails with the following output:
`openocd -f board/st_nucleo_f7.cfg`
```
> flash write_image fw.elf 0x100000
Flash write discontinued at 0x081020c4, next section at 0x08120000
timed out while waiting for target halted
target halted due to debug-request, current mode: Handler HardFault
xPSR: 0x00000003 pc: 00000000 msp: 0xffffffe0
error waiting for target flash write algorithm
error writing to flash at address 0x08000000 at offset 0x00100000
```
This is using the embedded `ST-LINK` included on the nucleo. The st-link
firmware version is `V2J31M21`.
`fw.elf` has sections starting in bank1 of flash, which is why the offset is
only the difference between bank1 and bank2.
The banks refered to here are banks in the stm32f7x sense, and are _not_
openocd flash banks.
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