Hi,
On Sun, 2008-10-12 at 19:38 +0200, Øyvind Harboe wrote:
> I was not able to apply this patch cleanly.
I just took the original 2 patches and used 'patch -p0 < xxx.patch' to
apply them to trunk and they applied cleanly. Here is the 'svn diff'
patch of the result.
I'm really curious why this didn't work for you though.
Cheers,
John McCarthy.
Index: src/target/mips_ejtag.c
===================================================================
--- src/target/mips_ejtag.c (revision 1047)
+++ src/target/mips_ejtag.c (working copy)
@@ -194,18 +194,19 @@
int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
{
+ u32 ejtag_ctrl;
jtag_add_end_state(TAP_RTI);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
/* set debug break bit */
- ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK;
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+ ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* break bit will be cleared by hardware */
- ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
- LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
- if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl);
+ if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
LOG_DEBUG("Failed to enter Debug Mode!");
return ERROR_OK;
Index: src/target/mips32_pracc.c
===================================================================
--- src/target/mips32_pracc.c (revision 1047)
+++ src/target/mips32_pracc.c (working copy)
@@ -47,7 +47,7 @@
while (1)
{
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_PRACC)
break;
@@ -61,8 +61,9 @@
static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address)
{
+ mips_ejtag_t *ejtag_info = ctx->ejtag_info;
int offset;
- u32 ctrl, data;
+ u32 ejtag_ctrl, data;
if ((address >= MIPS32_PRACC_PARAM_IN)
&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -102,25 +103,26 @@
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear the access pending bit (let the processor eat!) */
- ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+ mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
return ERROR_OK;
}
static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address)
{
- u32 ctrl,data;
+ u32 ejtag_ctrl,data;
int offset;
+ mips_ejtag_t *ejtag_info = ctx->ejtag_info;
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear access pending bit */
- ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+ mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
if ((address >= MIPS32_PRACC_PARAM_IN)
&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -150,7 +152,7 @@
int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int num_param_in, u32 *param_in, int num_param_out, u32 *param_out, int cycle)
{
- u32 ctrl;
+ u32 ejtag_ctrl;
u32 address, data;
mips32_pracc_context ctx;
int retval;
@@ -167,7 +169,7 @@
while (1)
{
- if ((retval = wait_for_pracc_rw(ejtag_info, &ctrl)) != ERROR_OK)
+ if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
address = data = 0;
@@ -175,7 +177,7 @@
mips_ejtag_drscan_32(ejtag_info, &address);
/* Check for read or write */
- if (ctrl & EJTAG_CTRL_PRNW)
+ if (ejtag_ctrl & EJTAG_CTRL_PRNW)
{
if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK)
return retval;
Index: src/target/mips32_dmaacc.c
===================================================================
--- src/target/mips32_dmaacc.c (revision 1047)
+++ src/target/mips32_dmaacc.c (working copy)
@@ -44,7 +44,7 @@
static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read:
@@ -56,14 +56,14 @@
// Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -71,9 +71,9 @@
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
@@ -88,7 +88,7 @@
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read_h:
@@ -100,14 +100,14 @@
// Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -115,9 +115,9 @@
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
@@ -136,7 +136,7 @@
static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read_b:
@@ -148,14 +148,14 @@
// Initiate DMA Read & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Read Data
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -163,9 +163,9 @@
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
@@ -188,7 +188,7 @@
static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_write:
@@ -205,20 +205,20 @@
// Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
@@ -233,7 +233,7 @@
static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
@@ -255,20 +255,20 @@
// Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
@@ -283,7 +283,7 @@
static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
{
u32 v;
- u32 ctrl_reg;
+ u32 ejtag_ctrl;
int retries = RETRY_ATTEMPTS;
@@ -306,20 +306,20 @@
// Initiate DMA Write & set DSTRT
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
// Wait for DSTRT to Clear
do {
- ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+ ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
// Clear DMA & Check DERR
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
- mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
- if (ctrl_reg & EJTAG_CTRL_DERR)
+ ejtag_ctrl = ejtag_info->ejtag_ctrl;
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (ejtag_ctrl & EJTAG_CTRL_DERR)
{
if (retries--) {
printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
Index: src/target/mips32_dmaacc.h
===================================================================
--- src/target/mips32_dmaacc.h (revision 1047)
+++ src/target/mips32_dmaacc.h (working copy)
@@ -32,7 +32,7 @@
#define EJTAG_CTRL_DMA_WORD 0x00000100
#define EJTAG_CTRL_DMA_TRIPLEBYTE 0x00000180
-#define RETRY_ATTEMPTS 4
+#define RETRY_ATTEMPTS 0
extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
Index: src/target/mips_m4k.c
===================================================================
--- src/target/mips_m4k.c (revision 1047)
+++ src/target/mips_m4k.c (working copy)
@@ -132,13 +132,14 @@
int retval;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
jtag_add_end_state(TAP_RTI);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
- if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
+ if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
@@ -167,19 +168,19 @@
target->state = TARGET_RUNNING;
}
- if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
+ if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI);
- ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
+ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
-// LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
+// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
return ERROR_OK;
}
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