Hey all,
I've created two patches in response to this thread about typedefs
versus structs. Both contain the same documentation updates, but one
makes everything 'struct target_s' while the other makes everything
'target_t'. The patches are also updated for head.
// Dean Glazeski
David Brownell wrote:
On Tuesday 19 May 2009, Dean Glazeski wrote:
changed all 'struct target_s' to 'target_t' to keep things consistent.
I'd rather do away with all typedefs myself, except maybe
for "int" variants. Ditto that "*_t" convention.
Anyone feel strongly pro-typedef?
Index: arm7_9_common.c
===================================================================
--- arm7_9_common.c (revision 1858)
+++ arm7_9_common.c (working copy)
@@ -37,7 +37,7 @@
#include "arm_simulator.h"
-int arm7_9_debug_entry(target_t *target);
+int arm7_9_debug_entry(struct target_s *target);
int arm7_9_enable_sw_bkpts(struct target_s *target);
/* command handler forward declarations */
@@ -162,7 +162,7 @@
* @param target Pointer to an ARM7/9 target to setup
* @return Result of clearing the watchpoints on the target
*/
-int arm7_9_setup(target_t *target)
+int arm7_9_setup(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -182,7 +182,7 @@
* targets
* @return ERROR_OK if successful
*/
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p,
arm7_9_common_t **arm7_9_p)
+int arm7_9_get_arch_pointers(struct target_s *target, armv4_5_common_t
**armv4_5_p, arm7_9_common_t **arm7_9_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -773,7 +773,15 @@
return ERROR_OK;
}
-int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
+/**
+ * Get some data from the ARM7/9 target.
+ *
+ * @param target Pointer to the ARM7/9 target to read data from
+ * @param size The number of 32bit words to be read
+ * @param buffer Pointer to the buffer that will hold the data
+ * @return The result of receiving data from the Embedded ICE unit
+ */
+int arm7_9_target_request_data(struct target_s *target, u32 size, u8 *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -786,6 +794,7 @@
retval = embeddedice_receive(jtag_info, data, size);
+ /* return the 32-bit ints in the 8-bit array */
for (i = 0; i < size; i++)
{
h_u32_to_le(buffer + (i * 4), data[i]);
@@ -796,10 +805,19 @@
return retval;
}
+/**
+ * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
+ * target is running and the DCC control register has the W bit high, this will
+ * execute the request on the target.
+ *
+ * @param priv Void pointer expected to be a struct target_s pointer
+ * @return ERROR_OK unless there are issues with the JTAG queue or when reading
+ * from the Embedded ICE unit
+ */
int arm7_9_handle_target_request(void *priv)
{
int retval = ERROR_OK;
- target_t *target = priv;
+ struct target_s *target = priv;
if (!target->type->examined)
return ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -838,7 +856,27 @@
return ERROR_OK;
}
-int arm7_9_poll(target_t *target)
+/**
+ * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
+ * is manipulated to the right halted state based on its current state. This
is
+ * what happens:
+ *
+ * <table>
+ * <tr><th>State</th><th>Action</th></tr>
+ * <tr><td>TARGET_RUNNING | TARGET_RESET</td><td>Enters debug
mode. If TARGET_RESET, pc may be checked</td></tr>
+ * <tr><td>TARGET_UNKNOWN</td><td>Warning is logged</td></tr>
+ * <tr><td>TARGET_DEBUG_RUNNING</td><td>Enters debug mode</td></tr>
+ * <tr><td>TARGET_HALTED</td><td>Nothing</td></tr>
+ * </table>
+ *
+ * If the target does not end up in the halted state, a warning is produced.
If
+ * DBGACK is cleared, then the target is expected to either be running or
+ * running in debug.
+ *
+ * @param target Pointer to the ARM7/9 target to poll
+ * @return ERROR_OK or an error status if a command fails
+ */
+int arm7_9_poll(struct target_s *target)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -907,7 +945,7 @@
}
if (target->state != TARGET_HALTED)
{
- LOG_WARNING("DBGACK set, but the target did not end up
in the halted stated %d", target->state);
+ LOG_WARNING("DBGACK set, but the target did not end up
in the halted state %d", target->state);
}
}
else
@@ -919,15 +957,18 @@
return ERROR_OK;
}
-/*
- Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
- in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
- while the core is held in reset(SRST). It isn't possible to program the halt
- condition once reset was asserted, hence a hook that allows the target to set
- up its reset-halt condition prior to asserting reset.
-*/
-
-int arm7_9_assert_reset(target_t *target)
+/**
+ * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
+ * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
+ * affected) completely stop the JTAG clock while the core is held in reset
+ * (SRST). It isn't possible to program the halt condition once reset is
+ * asserted, hence a hook that allows the target to set up its reset-halt
+ * condition is setup prior to asserting reset.
+ *
+ * @param target Pointer to an ARM7/9 target to assert reset on
+ * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
+ */
+int arm7_9_assert_reset(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -965,7 +1006,7 @@
}
}
- /* here we should issue a srst only, but we may have to assert trst as
well */
+ /* here we should issue an SRST only, but we may have to assert TRST as
well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
@@ -988,7 +1029,16 @@
return ERROR_OK;
}
-int arm7_9_deassert_reset(target_t *target)
+/**
+ * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
+ * and the target is being reset into a halt, a warning will be triggered
+ * because it is not possible to reset into a halted mode in this case. The
+ * target is halted using the target's functions.
+ *
+ * @param target Pointer to the target to have the reset deasserted
+ * @return ERROR_OK or an error from polling or halting the target
+ */
+int arm7_9_deassert_reset(struct target_s *target)
{
int retval=ERROR_OK;
LOG_DEBUG("target->state: %s",
@@ -1018,7 +1068,16 @@
return retval;
}
-int arm7_9_clear_halt(target_t *target)
+/**
+ * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
+ * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
+ * vector catch was used, it is restored. Otherwise, the control value is
+ * restored and the watchpoint unit is restored if it was in use.
+ *
+ * @param target Pointer to the ARM7/9 target to have halt cleared
+ * @return Always ERROR_OK
+ */
+int arm7_9_clear_halt(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1066,6 +1125,16 @@
return ERROR_OK;
}
+/**
+ * Issue a software reset and halt to an ARM7/9 target. The target is halted
+ * and then there is a wait until the processor shows the halt. This wait can
+ * timeout and results in an error being returned. The software reset involves
+ * clearing the halt, updating the debug control register, changing to ARM
mode,
+ * reset of the program counter, and reset of all of the registers.
+ *
+ * @param target Pointer to the ARM7/9 target to be reset and halted by
software
+ * @return Error status if any of the commands fail, otherwise ERROR_OK
+ */
int arm7_9_soft_reset_halt(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1163,7 +1232,16 @@
return ERROR_OK;
}
-int arm7_9_halt(target_t *target)
+/**
+ * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
+ * line or by programming a watchpoint to trigger on any address. It is
+ * considered a bug to call this function while the target is in the
+ * TARGET_RESET state.
+ *
+ * @param target Pointer to the ARM7/9 target to be halted
+ * @return Always ERROR_OK
+ */
+int arm7_9_halt(struct target_s *target)
{
if (target->state==TARGET_RESET)
{
@@ -1215,7 +1293,18 @@
return ERROR_OK;
}
-int arm7_9_debug_entry(target_t *target)
+/**
+ * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
+ * ARM. The JTAG queue is then executed and the reason for debug entry is
+ * examined. Once done, the target is verified to be halted and the processor
+ * is forced into ARM mode. The core registers are saved for the current core
+ * mode and the program counter (register 15) is updated as needed. The core
+ * registers and CPSR and SPSR are saved for restoration later.
+ *
+ * @param target Pointer to target that is entering debug mode
+ * @return Error code if anything fails, otherwise ERROR_OK
+ */
+int arm7_9_debug_entry(struct target_s *target)
{
int i;
u32 context[16];
@@ -1376,7 +1465,16 @@
return ERROR_OK;
}
-int arm7_9_full_context(target_t *target)
+/**
+ * Validate the full context for an ARM7/9 target in all processor modes. If
+ * there are any invalid registers for the target, they will all be read. This
+ * includes the PSR.
+ *
+ * @param target Pointer to the ARM7/9 target to capture the full context from
+ * @return Error if the target is not halted, has an invalid core mode, or if
+ * the JTAG queue fails to execute
+ */
+int arm7_9_full_context(struct target_s *target)
{
int i;
int retval;
@@ -1457,7 +1555,19 @@
return ERROR_OK;
}
-int arm7_9_restore_context(target_t *target)
+/**
+ * Restore the processor context on an ARM7/9 target. The full processor
+ * context is analyzed to see if any of the registers are dirty on this end,
but
+ * have a valid new value. If this is the case, the processor is changed to
the
+ * appropriate mode and the new register values are written out to the
+ * processor. If there happens to be a dirty register with an invalid value,
an
+ * error will be logged.
+ *
+ * @param target Pointer to the ARM7/9 target to have its context restored
+ * @return Error status if the target is not halted or the core mode in the
+ * armv4_5 struct is invalid.
+ */
+int arm7_9_restore_context(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1599,6 +1709,14 @@
return ERROR_OK;
}
+/**
+ * Restart the core of an ARM7/9 target. A RESTART command is sent to the
+ * instruction register and the JTAG state is set to TAP_IDLE causing a core
+ * restart.
+ *
+ * @param target Pointer to the ARM7/9 target to be restarted
+ * @return Result of executing the JTAG queue
+ */
int arm7_9_restart_core(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1617,6 +1735,12 @@
return jtag_execute_queue();
}
+/**
+ * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
+ * iterated through and are set on the target if they aren't already set.
+ *
+ * @param target Pointer to the ARM7/9 target to enable watchpoints on
+ */
void arm7_9_enable_watchpoints(struct target_s *target)
{
watchpoint_t *watchpoint = target->watchpoints;
@@ -1629,6 +1753,12 @@
}
}
+/**
+ * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
+ * iterated through and are set on the target.
+ *
+ * @param target Pointer to the ARM7/9 target to enable breakpoints on
+ */
void arm7_9_enable_breakpoints(struct target_s *target)
{
breakpoint_t *breakpoint = target->breakpoints;
@@ -1801,7 +1931,7 @@
return ERROR_OK;
}
-void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
+void arm7_9_enable_eice_step(struct target_s *target, u32 next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1839,7 +1969,7 @@
}
}
-void arm7_9_disable_eice_step(target_t *target)
+void arm7_9_disable_eice_step(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2490,7 +2620,7 @@
int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params,
mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32
entry_point, u32 exit_point, int timeout_ms, void *arch_info, int
(*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void
*arch_info));
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8
*buffer)
+int arm7_9_bulk_write_memory(struct target_s *target, u32 address, u32 count,
u8 *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2733,7 +2863,7 @@
u32 value;
int spsr;
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2778,7 +2908,7 @@
int rotate;
int spsr;
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2819,7 +2949,7 @@
u32 value;
u32 mode;
int num;
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2850,7 +2980,7 @@
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd,
char **args, int argc)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2883,7 +3013,7 @@
int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx, char *cmd, char **args, int argc)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2916,7 +3046,7 @@
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target_s *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -2947,7 +3077,7 @@
return ERROR_OK;
}
-int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
+int arm7_9_init_arch_info(struct target_s *target, arm7_9_common_t *arm7_9)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
Index: arm7_9_common.h
===================================================================
--- arm7_9_common.h (revision 1858)
+++ arm7_9_common.h (working copy)
@@ -32,76 +32,79 @@
#include "breakpoints.h"
#include "etm.h"
-#define ARM7_9_COMMON_MAGIC 0x0a790a79
+#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
+/**
+ * Structure for items that are common between both ARM7 and ARM9 targets.
+ */
typedef struct arm7_9_common_s
{
u32 common_magic;
- arm_jtag_t jtag_info;
- reg_cache_t *eice_cache;
+ arm_jtag_t jtag_info; /**< JTAG information for target */
+ reg_cache_t *eice_cache; /**< Embedded ICE register cache */
- u32 arm_bkpt;
- u16 thumb_bkpt;
- int sw_breakpoints_added;
- int breakpoint_count;
- int wp_available;
- int wp_available_max;
- int wp0_used;
- int wp1_used;
- int wp1_used_default;
+ u32 arm_bkpt; /**< ARM breakpoint instruction */
+ u16 thumb_bkpt; /**< Thumb breakpoint instruction */
+ int sw_breakpoints_added; /**< Specifies which watchpoint software
breakpoints are setup on */
+ int breakpoint_count; /**< Current number of set breakpoints */
+ int wp_available; /**< Current number of available watchpoint units */
+ int wp_available_max; /**< Maximum number of available watchpoint units
*/
+ int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
+ int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
+ int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is
used by default */
int force_hw_bkpts;
- int dbgreq_adjust_pc;
- int use_dbgrq;
- int need_bypass_before_restart;
+ int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
+ int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the
target */
+ int need_bypass_before_restart; /**< Specifies if there should be a
bypass before a JTAG restart */
etm_context_t *etm_ctx;
int has_single_step;
int has_monitor_mode;
- int has_vector_catch;
+ int has_vector_catch; /**< Specifies if the target has a reset vector
catch */
- int debug_entry_from_reset;
+ int debug_entry_from_reset; /**< Specifies if debug entry was from a
reset */
struct working_area_s *dcc_working_area;
int fast_memory_access;
int dcc_downloads;
- int (*examine_debug_reason)(target_t *target);
+ int (*examine_debug_reason)(struct target_s *target); /**< Function for
determining why debug state was entered */
- void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
+ void (*change_to_arm)(struct target_s *target, u32 *r0, u32 *pc); /**<
Function for changing from Thumb to ARM mode */
- void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
- void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void
*buffer, int size);
- void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
+ void (*read_core_regs)(struct target_s *target, u32 mask, u32
*core_regs[16]); /**< Function for reading the core registers */
+ void (*read_core_regs_target_buffer)(struct target_s *target, u32 mask,
void *buffer, int size);
+ void (*read_xpsr)(struct target_s *target, u32 *xpsr, int spsr); /**<
Function for reading CPSR or SPSR */
- void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
- void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
- void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+ void (*write_xpsr)(struct target_s *target, u32 xpsr, int spsr); /**<
Function for writing to CPSR or SPSR */
+ void (*write_xpsr_im8)(struct target_s *target, u8 xpsr_im, int rot,
int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
+ void (*write_core_regs)(struct target_s *target, u32 mask, u32
core_regs[16]);
- void (*load_word_regs)(target_t *target, u32 mask);
- void (*load_hword_reg)(target_t *target, int num);
- void (*load_byte_reg)(target_t *target, int num);
+ void (*load_word_regs)(struct target_s *target, u32 mask);
+ void (*load_hword_reg)(struct target_s *target, int num);
+ void (*load_byte_reg)(struct target_s *target, int num);
- void (*store_word_regs)(target_t *target, u32 mask);
- void (*store_hword_reg)(target_t *target, int num);
- void (*store_byte_reg)(target_t *target, int num);
+ void (*store_word_regs)(struct target_s *target, u32 mask);
+ void (*store_hword_reg)(struct target_s *target, int num);
+ void (*store_byte_reg)(struct target_s *target, int num);
- void (*write_pc)(target_t *target, u32 pc);
- void (*branch_resume)(target_t *target);
- void (*branch_resume_thumb)(target_t *target);
+ void (*write_pc)(struct target_s *target, u32 pc); /**< Function for
writing to the program counter */
+ void (*branch_resume)(struct target_s *target);
+ void (*branch_resume_thumb)(struct target_s *target);
- void (*enable_single_step)(target_t *target, u32 next_pc);
- void (*disable_single_step)(target_t *target);
+ void (*enable_single_step)(struct target_s *target, u32 next_pc);
+ void (*disable_single_step)(struct target_s *target);
- void (*set_special_dbgrq)(target_t *target);
+ void (*set_special_dbgrq)(struct target_s *target); /**< Function for
setting DBGRQ if the normal way won't work */
- void (*pre_debug_entry)(target_t *target);
- void (*post_debug_entry)(target_t *target);
+ void (*pre_debug_entry)(struct target_s *target); /**< Callback
function called before entering debug mode */
+ void (*post_debug_entry)(struct target_s *target); /**< Callback
function called after entering debug mode */
- void (*pre_restore_context)(target_t *target);
- void (*post_restore_context)(target_t *target);
+ void (*pre_restore_context)(struct target_s *target); /**< Callback
function called before restoring the processor context */
+ void (*post_restore_context)(struct target_s *target); /**< Callback
function called after restoring the processor context */
armv4_5_common_t armv4_5_common;
void *arch_info;
@@ -110,27 +113,27 @@
int arm7_9_register_commands(struct command_context_s *cmd_ctx);
-int arm7_9_poll(target_t *target);
+int arm7_9_poll(struct target_s *target);
-int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
+int arm7_9_target_request_data(struct target_s *target, u32 size, u8 *buffer);
-int arm7_9_setup(target_t *target);
-int arm7_9_assert_reset(target_t *target);
-int arm7_9_deassert_reset(target_t *target);
-int arm7_9_reset_request_halt(target_t *target);
-int arm7_9_early_halt(target_t *target);
+int arm7_9_setup(struct target_s *target);
+int arm7_9_assert_reset(struct target_s *target);
+int arm7_9_deassert_reset(struct target_s *target);
+int arm7_9_reset_request_halt(struct target_s *target);
+int arm7_9_early_halt(struct target_s *target);
int arm7_9_soft_reset_halt(struct target_s *target);
int arm7_9_prepare_reset_halt(struct target_s *target);
-int arm7_9_halt(target_t *target);
-int arm7_9_full_context(target_t *target);
-int arm7_9_restore_context(target_t *target);
+int arm7_9_halt(struct target_s *target);
+int arm7_9_full_context(struct target_s *target);
+int arm7_9_restore_context(struct target_s *target);
int arm7_9_resume(struct target_s *target, int current, u32 address, int
handle_breakpoints, int debug_execution);
int arm7_9_step(struct target_s *target, int current, u32 address, int
handle_breakpoints);
int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode
mode);
int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer);
int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer);
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8
*buffer);
+int arm7_9_bulk_write_memory(struct target_s *target, u32 address, u32 count,
u8 *buffer);
int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count,
u32* checksum);
int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count,
u32* blank);
@@ -141,12 +144,12 @@
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t
*watchpoint);
-void arm7_9_enable_eice_step(target_t *target, u32 next_pc);
-void arm7_9_disable_eice_step(target_t *target);
+void arm7_9_enable_eice_step(struct target_s *target, u32 next_pc);
+void arm7_9_disable_eice_step(struct target_s *target);
int arm7_9_execute_sys_speed(struct target_s *target);
-int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p,
arm7_9_common_t **arm7_9_p);
+int arm7_9_init_arch_info(struct target_s *target, arm7_9_common_t *arm7_9);
+int arm7_9_get_arch_pointers(struct target_s *target, armv4_5_common_t
**armv4_5_p, arm7_9_common_t **arm7_9_p);
#endif /* ARM7_9_COMMON_H */
Index: arm7_9_common.c
===================================================================
--- arm7_9_common.c (revision 1858)
+++ arm7_9_common.c (working copy)
@@ -38,7 +38,7 @@
int arm7_9_debug_entry(target_t *target);
-int arm7_9_enable_sw_bkpts(struct target_s *target);
+int arm7_9_enable_sw_bkpts(target_t *target);
/* command handler forward declarations */
int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char
*cmd, char **args, int argc);
@@ -214,7 +214,7 @@
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_set_breakpoint(target_t *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -336,7 +336,7 @@
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_unset_breakpoint(target_t *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
@@ -412,7 +412,7 @@
* @return An error status if there is a problem adding the breakpoint or the
* result of setting the breakpoint
*/
-int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_add_breakpoint(target_t *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -463,7 +463,7 @@
* @return Error status if there was a problem unsetting the breakpoint or the
* watchpoints could not be cleared
*/
-int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_remove_breakpoint(target_t *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -500,7 +500,7 @@
* @return Error status if watchpoint set fails or the result of executing the
* JTAG queue
*/
-int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_set_watchpoint(target_t *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -572,7 +572,7 @@
* @return Error status while trying to unset the watchpoint or the result of
* executing the JTAG queue
*/
-int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_unset_watchpoint(target_t *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -621,7 +621,7 @@
* @param watchpoint Pointer to the watchpoint to be added
* @return Error status while trying to add the watchpoint
*/
-int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_add_watchpoint(target_t *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -655,7 +655,7 @@
* @param watchpoint Pointer to the watchpoint to be removed
* @return Result of trying to unset the watchpoint
*/
-int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_remove_watchpoint(target_t *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -683,7 +683,7 @@
* @return Error status if there is a timeout or a problem while executing the
* JTAG queue
*/
-int arm7_9_execute_sys_speed(struct target_s *target)
+int arm7_9_execute_sys_speed(target_t *target)
{
int retval;
@@ -736,7 +736,7 @@
* @param target Pointer to the target to issue commands to
* @return Always ERROR_OK
*/
-int arm7_9_execute_fast_sys_speed(struct target_s *target)
+int arm7_9_execute_fast_sys_speed(target_t *target)
{
static int set=0;
static u8 check_value[4], check_mask[4];
@@ -773,6 +773,14 @@
return ERROR_OK;
}
+/**
+ * Get some data from the ARM7/9 target.
+ *
+ * @param target Pointer to the ARM7/9 target to read data from
+ * @param size The number of 32bit words to be read
+ * @param buffer Pointer to the buffer that will hold the data
+ * @return The result of receiving data from the Embedded ICE unit
+ */
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -786,6 +794,7 @@
retval = embeddedice_receive(jtag_info, data, size);
+ /* return the 32-bit ints in the 8-bit array */
for (i = 0; i < size; i++)
{
h_u32_to_le(buffer + (i * 4), data[i]);
@@ -796,6 +805,15 @@
return retval;
}
+/**
+ * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
+ * target is running and the DCC control register has the W bit high, this will
+ * execute the request on the target.
+ *
+ * @param priv Void pointer expected to be a target_t pointer
+ * @return ERROR_OK unless there are issues with the JTAG queue or when reading
+ * from the Embedded ICE unit
+ */
int arm7_9_handle_target_request(void *priv)
{
int retval = ERROR_OK;
@@ -838,6 +856,26 @@
return ERROR_OK;
}
+/**
+ * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
+ * is manipulated to the right halted state based on its current state. This
is
+ * what happens:
+ *
+ * <table>
+ * <tr><th>State</th><th>Action</th></tr>
+ * <tr><td>TARGET_RUNNING | TARGET_RESET</td><td>Enters debug
mode. If TARGET_RESET, pc may be checked</td></tr>
+ * <tr><td>TARGET_UNKNOWN</td><td>Warning is logged</td></tr>
+ * <tr><td>TARGET_DEBUG_RUNNING</td><td>Enters debug mode</td></tr>
+ * <tr><td>TARGET_HALTED</td><td>Nothing</td></tr>
+ * </table>
+ *
+ * If the target does not end up in the halted state, a warning is produced.
If
+ * DBGACK is cleared, then the target is expected to either be running or
+ * running in debug.
+ *
+ * @param target Pointer to the ARM7/9 target to poll
+ * @return ERROR_OK or an error status if a command fails
+ */
int arm7_9_poll(target_t *target)
{
int retval;
@@ -907,7 +945,7 @@
}
if (target->state != TARGET_HALTED)
{
- LOG_WARNING("DBGACK set, but the target did not end up
in the halted stated %d", target->state);
+ LOG_WARNING("DBGACK set, but the target did not end up
in the halted state %d", target->state);
}
}
else
@@ -919,14 +957,17 @@
return ERROR_OK;
}
-/*
- Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
- in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
- while the core is held in reset(SRST). It isn't possible to program the halt
- condition once reset was asserted, hence a hook that allows the target to set
- up its reset-halt condition prior to asserting reset.
-*/
-
+/**
+ * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
+ * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
+ * affected) completely stop the JTAG clock while the core is held in reset
+ * (SRST). It isn't possible to program the halt condition once reset is
+ * asserted, hence a hook that allows the target to set up its reset-halt
+ * condition is setup prior to asserting reset.
+ *
+ * @param target Pointer to an ARM7/9 target to assert reset on
+ * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
+ */
int arm7_9_assert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -965,7 +1006,7 @@
}
}
- /* here we should issue a srst only, but we may have to assert trst as
well */
+ /* here we should issue an SRST only, but we may have to assert TRST as
well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
@@ -988,6 +1029,15 @@
return ERROR_OK;
}
+/**
+ * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
+ * and the target is being reset into a halt, a warning will be triggered
+ * because it is not possible to reset into a halted mode in this case. The
+ * target is halted using the target's functions.
+ *
+ * @param target Pointer to the target to have the reset deasserted
+ * @return ERROR_OK or an error from polling or halting the target
+ */
int arm7_9_deassert_reset(target_t *target)
{
int retval=ERROR_OK;
@@ -1018,6 +1068,15 @@
return retval;
}
+/**
+ * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
+ * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
+ * vector catch was used, it is restored. Otherwise, the control value is
+ * restored and the watchpoint unit is restored if it was in use.
+ *
+ * @param target Pointer to the ARM7/9 target to have halt cleared
+ * @return Always ERROR_OK
+ */
int arm7_9_clear_halt(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1066,7 +1125,17 @@
return ERROR_OK;
}
-int arm7_9_soft_reset_halt(struct target_s *target)
+/**
+ * Issue a software reset and halt to an ARM7/9 target. The target is halted
+ * and then there is a wait until the processor shows the halt. This wait can
+ * timeout and results in an error being returned. The software reset involves
+ * clearing the halt, updating the debug control register, changing to ARM
mode,
+ * reset of the program counter, and reset of all of the registers.
+ *
+ * @param target Pointer to the ARM7/9 target to be reset and halted by
software
+ * @return Error status if any of the commands fail, otherwise ERROR_OK
+ */
+int arm7_9_soft_reset_halt(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1163,6 +1232,15 @@
return ERROR_OK;
}
+/**
+ * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
+ * line or by programming a watchpoint to trigger on any address. It is
+ * considered a bug to call this function while the target is in the
+ * TARGET_RESET state.
+ *
+ * @param target Pointer to the ARM7/9 target to be halted
+ * @return Always ERROR_OK
+ */
int arm7_9_halt(target_t *target)
{
if (target->state==TARGET_RESET)
@@ -1215,6 +1293,17 @@
return ERROR_OK;
}
+/**
+ * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
+ * ARM. The JTAG queue is then executed and the reason for debug entry is
+ * examined. Once done, the target is verified to be halted and the processor
+ * is forced into ARM mode. The core registers are saved for the current core
+ * mode and the program counter (register 15) is updated as needed. The core
+ * registers and CPSR and SPSR are saved for restoration later.
+ *
+ * @param target Pointer to target that is entering debug mode
+ * @return Error code if anything fails, otherwise ERROR_OK
+ */
int arm7_9_debug_entry(target_t *target)
{
int i;
@@ -1376,6 +1465,15 @@
return ERROR_OK;
}
+/**
+ * Validate the full context for an ARM7/9 target in all processor modes. If
+ * there are any invalid registers for the target, they will all be read. This
+ * includes the PSR.
+ *
+ * @param target Pointer to the ARM7/9 target to capture the full context from
+ * @return Error if the target is not halted, has an invalid core mode, or if
+ * the JTAG queue fails to execute
+ */
int arm7_9_full_context(target_t *target)
{
int i;
@@ -1457,6 +1555,18 @@
return ERROR_OK;
}
+/**
+ * Restore the processor context on an ARM7/9 target. The full processor
+ * context is analyzed to see if any of the registers are dirty on this end,
but
+ * have a valid new value. If this is the case, the processor is changed to
the
+ * appropriate mode and the new register values are written out to the
+ * processor. If there happens to be a dirty register with an invalid value,
an
+ * error will be logged.
+ *
+ * @param target Pointer to the ARM7/9 target to have its context restored
+ * @return Error status if the target is not halted or the core mode in the
+ * armv4_5 struct is invalid.
+ */
int arm7_9_restore_context(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1599,7 +1709,15 @@
return ERROR_OK;
}
-int arm7_9_restart_core(struct target_s *target)
+/**
+ * Restart the core of an ARM7/9 target. A RESTART command is sent to the
+ * instruction register and the JTAG state is set to TAP_IDLE causing a core
+ * restart.
+ *
+ * @param target Pointer to the ARM7/9 target to be restarted
+ * @return Result of executing the JTAG queue
+ */
+int arm7_9_restart_core(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1617,7 +1735,13 @@
return jtag_execute_queue();
}
-void arm7_9_enable_watchpoints(struct target_s *target)
+/**
+ * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
+ * iterated through and are set on the target if they aren't already set.
+ *
+ * @param target Pointer to the ARM7/9 target to enable watchpoints on
+ */
+void arm7_9_enable_watchpoints(target_t *target)
{
watchpoint_t *watchpoint = target->watchpoints;
@@ -1629,7 +1753,13 @@
}
}
-void arm7_9_enable_breakpoints(struct target_s *target)
+/**
+ * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
+ * iterated through and are set on the target.
+ *
+ * @param target Pointer to the ARM7/9 target to enable breakpoints on
+ */
+void arm7_9_enable_breakpoints(target_t *target)
{
breakpoint_t *breakpoint = target->breakpoints;
@@ -1641,7 +1771,7 @@
}
}
-int arm7_9_resume(struct target_s *target, int current, u32 address, int
handle_breakpoints, int debug_execution)
+int arm7_9_resume(target_t *target, int current, u32 address, int
handle_breakpoints, int debug_execution)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1855,7 +1985,7 @@
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
-int arm7_9_step(struct target_s *target, int current, u32 address, int
handle_breakpoints)
+int arm7_9_step(target_t *target, int current, u32 address, int
handle_breakpoints)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1948,7 +2078,7 @@
return err;
}
-int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode
mode)
+int arm7_9_read_core_reg(target_t *target, int num, enum armv4_5_mode mode)
{
u32* reg_p[16];
u32 value;
@@ -2014,7 +2144,7 @@
return ERROR_OK;
}
-int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode
mode, u32 value)
+int arm7_9_write_core_reg(target_t *target, int num, enum armv4_5_mode mode,
u32 value)
{
u32 reg[16];
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2075,7 +2205,7 @@
return jtag_execute_queue();
}
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer)
+int arm7_9_read_memory(target_t *target, u32 address, u32 size, u32 count, u8
*buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2251,7 +2381,7 @@
return ERROR_OK;
}
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer)
+int arm7_9_write_memory(target_t *target, u32 address, u32 size, u32 count, u8
*buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2437,7 +2567,7 @@
static int dcc_count;
static u8 *dcc_buffer;
-static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int
timeout_ms, void *arch_info)
+static int arm7_9_dcc_completion(target_t *target, u32 exit_point, int
timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2488,7 +2618,7 @@
0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
};
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params,
mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32
entry_point, u32 exit_point, int timeout_ms, void *arch_info, int
(*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void
*arch_info));
+int armv4_5_run_algorithm_inner(target_t *target, int num_mem_params,
mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32
entry_point, u32 exit_point, int timeout_ms, void *arch_info, int
(*run_it)(target_t *target, u32 exit_point, int timeout_ms, void *arch_info));
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8
*buffer)
{
@@ -2556,7 +2686,7 @@
return retval;
}
-int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count,
u32* checksum)
+int arm7_9_checksum_memory(target_t *target, u32 address, u32 count, u32*
checksum)
{
working_area_t *crc_algorithm;
armv4_5_algorithm_t armv4_5_info;
@@ -2637,7 +2767,7 @@
return ERROR_OK;
}
-int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count,
u32* blank)
+int arm7_9_blank_check_memory(target_t *target, u32 address, u32 count, u32*
blank)
{
working_area_t *erase_check_algorithm;
reg_param_t reg_params[3];
Index: arm7_9_common.h
===================================================================
--- arm7_9_common.h (revision 1858)
+++ arm7_9_common.h (working copy)
@@ -32,52 +32,55 @@
#include "breakpoints.h"
#include "etm.h"
-#define ARM7_9_COMMON_MAGIC 0x0a790a79
+#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
+/**
+ * Structure for items that are common between both ARM7 and ARM9 targets.
+ */
typedef struct arm7_9_common_s
{
u32 common_magic;
- arm_jtag_t jtag_info;
- reg_cache_t *eice_cache;
+ arm_jtag_t jtag_info; /**< JTAG information for target */
+ reg_cache_t *eice_cache; /**< Embedded ICE register cache */
- u32 arm_bkpt;
- u16 thumb_bkpt;
- int sw_breakpoints_added;
- int breakpoint_count;
- int wp_available;
- int wp_available_max;
- int wp0_used;
- int wp1_used;
- int wp1_used_default;
+ u32 arm_bkpt; /**< ARM breakpoint instruction */
+ u16 thumb_bkpt; /**< Thumb breakpoint instruction */
+ int sw_breakpoints_added; /**< Specifies which watchpoint software
breakpoints are setup on */
+ int breakpoint_count; /**< Current number of set breakpoints */
+ int wp_available; /**< Current number of available watchpoint units */
+ int wp_available_max; /**< Maximum number of available watchpoint units
*/
+ int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
+ int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
+ int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is
used by default */
int force_hw_bkpts;
- int dbgreq_adjust_pc;
- int use_dbgrq;
- int need_bypass_before_restart;
+ int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
+ int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the
target */
+ int need_bypass_before_restart; /**< Specifies if there should be a
bypass before a JTAG restart */
etm_context_t *etm_ctx;
int has_single_step;
int has_monitor_mode;
- int has_vector_catch;
+ int has_vector_catch; /**< Specifies if the target has a reset vector
catch */
- int debug_entry_from_reset;
+ int debug_entry_from_reset; /**< Specifies if debug entry was from a
reset */
struct working_area_s *dcc_working_area;
int fast_memory_access;
int dcc_downloads;
- int (*examine_debug_reason)(target_t *target);
+ int (*examine_debug_reason)(target_t *target); /**< Function for
determining why debug state was entered */
- void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
+ void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc); /**<
Function for changing from Thumb to ARM mode */
- void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
+ void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
/**< Function for reading the core registers */
void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void
*buffer, int size);
- void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
+ void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function
for reading CPSR or SPSR */
- void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
- void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
+ void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function
for writing to CPSR or SPSR */
+ void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int
spsr); /**< Function for writing an immediate value to CPSR or SPSR */
void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
void (*load_word_regs)(target_t *target, u32 mask);
@@ -88,20 +91,20 @@
void (*store_hword_reg)(target_t *target, int num);
void (*store_byte_reg)(target_t *target, int num);
- void (*write_pc)(target_t *target, u32 pc);
+ void (*write_pc)(target_t *target, u32 pc); /**< Function for writing
to the program counter */
void (*branch_resume)(target_t *target);
void (*branch_resume_thumb)(target_t *target);
void (*enable_single_step)(target_t *target, u32 next_pc);
void (*disable_single_step)(target_t *target);
- void (*set_special_dbgrq)(target_t *target);
+ void (*set_special_dbgrq)(target_t *target); /**< Function for setting
DBGRQ if the normal way won't work */
- void (*pre_debug_entry)(target_t *target);
- void (*post_debug_entry)(target_t *target);
+ void (*pre_debug_entry)(target_t *target); /**< Callback function
called before entering debug mode */
+ void (*post_debug_entry)(target_t *target); /**< Callback function
called after entering debug mode */
- void (*pre_restore_context)(target_t *target);
- void (*post_restore_context)(target_t *target);
+ void (*pre_restore_context)(target_t *target); /**< Callback function
called before restoring the processor context */
+ void (*post_restore_context)(target_t *target); /**< Callback function
called after restoring the processor context */
armv4_5_common_t armv4_5_common;
void *arch_info;
@@ -119,32 +122,32 @@
int arm7_9_deassert_reset(target_t *target);
int arm7_9_reset_request_halt(target_t *target);
int arm7_9_early_halt(target_t *target);
-int arm7_9_soft_reset_halt(struct target_s *target);
-int arm7_9_prepare_reset_halt(struct target_s *target);
+int arm7_9_soft_reset_halt(target_t *target);
+int arm7_9_prepare_reset_halt(target_t *target);
int arm7_9_halt(target_t *target);
int arm7_9_full_context(target_t *target);
int arm7_9_restore_context(target_t *target);
-int arm7_9_resume(struct target_s *target, int current, u32 address, int
handle_breakpoints, int debug_execution);
-int arm7_9_step(struct target_s *target, int current, u32 address, int
handle_breakpoints);
-int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode
mode);
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer);
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer);
+int arm7_9_resume(target_t *target, int current, u32 address, int
handle_breakpoints, int debug_execution);
+int arm7_9_step(target_t *target, int current, u32 address, int
handle_breakpoints);
+int arm7_9_read_core_reg(target_t *target, int num, enum armv4_5_mode mode);
+int arm7_9_read_memory(target_t *target, u32 address, u32 size, u32 count, u8
*buffer);
+int arm7_9_write_memory(target_t *target, u32 address, u32 size, u32 count, u8
*buffer);
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8
*buffer);
-int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count,
u32* checksum);
-int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count,
u32* blank);
+int arm7_9_checksum_memory(target_t *target, u32 address, u32 count, u32*
checksum);
+int arm7_9_blank_check_memory(target_t *target, u32 address, u32 count, u32*
blank);
-int arm7_9_run_algorithm(struct target_s *target, int num_mem_params,
mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32
entry_point, void *arch_info);
+int arm7_9_run_algorithm(target_t *target, int num_mem_params, mem_param_t
*mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void
*arch_info);
-int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t
*breakpoint);
-int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t
*watchpoint);
+int arm7_9_add_breakpoint(target_t *target, breakpoint_t *breakpoint);
+int arm7_9_remove_breakpoint(target_t *target, breakpoint_t *breakpoint);
+int arm7_9_add_watchpoint(target_t *target, watchpoint_t *watchpoint);
+int arm7_9_remove_watchpoint(target_t *target, watchpoint_t *watchpoint);
void arm7_9_enable_eice_step(target_t *target, u32 next_pc);
void arm7_9_disable_eice_step(target_t *target);
-int arm7_9_execute_sys_speed(struct target_s *target);
+int arm7_9_execute_sys_speed(target_t *target);
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p,
arm7_9_common_t **arm7_9_p);
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