On Mon, May 25, 2009 at 6:39 PM, David Brownell <davi...@pacbell.net> wrote:
> > > > When I do scan_chain > > > I get both imx27.bs and imx27.cpu which looks normal. > > Maybe for i.MX27 ... having a separate TAP for boundary > scan seems unusual to me. > > ISTR that most ARM cores are set up so that they have an > integrator-provided scan chain (plus the EmbeddedICE, > maybe an ETM, etc), conventionally for boundary scan. > > And several TI chips have their boundary scan hanging off > the IcePICK, a.k.a. "JTAG Routing Controller" (JRC), so > it's accessible even when the various ARM and DSP cores > aren't switched into the scan chain. > > > Re how to do it ... I'd kind of hope that a key step > would be throwing a BSDL file into the OpenOCD config, > since making *use* of the boundary scan involves info > that's in that file. Example, knowing which registers > to use, how big they are, what the bit semantics are, > what instruction opcodes are involved, etc. > > - Dave > > I don't see a BSDL file for the imx27. What information do we need? Maybe I could pull it from somewhere elsee? In a 1720 page reference manual all it says is: 7.7 Boundary Scan Register The boundary scan register (BSR) in the i.MX27 JTAG implementation contains bits for all device signals and clock pins and associated control signals. All i.MX27 bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register. But it doesn't give an address or anything else. thanks, Paul
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