Take #3 committed w/docs.
--
Øyvind Harboe
Embedded software and hardware consulting services
http://www.zylin.com
### Eclipse Workspace Patch 1.0
#P openocd
Index: src/jtag/jtag.h
===================================================================
--- src/jtag/jtag.h (revision 2714)
+++ src/jtag/jtag.h (working copy)
@@ -277,6 +277,7 @@
RESET_TRST_PULLS_SRST = 0x8,
RESET_TRST_OPEN_DRAIN = 0x10,
RESET_SRST_PUSH_PULL = 0x20,
+ RESET_SRST_GATES_JTAG = 0x40,
};
enum reset_types jtag_get_reset_config(void);
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 2714)
+++ src/target/arm7_9_common.c (working copy)
@@ -1021,6 +1021,17 @@
return ERROR_FAIL;
}
+ /* at this point trst has been asserted/deasserted once. We want to
+ * program embedded ice while SRST is asserted, but some CPUs gate
+ * the JTAG clock while SRST is asserted
+ */
+ bool srst_asserted = false;
+ if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) &&
((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+ {
+ jtag_add_reset(0, 1);
+ srst_asserted = true;
+ }
+
if (target->reset_halt)
{
/*
@@ -1053,7 +1064,7 @@
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
- } else
+ } else if (!srst_asserted)
{
jtag_add_reset(0, 1);
}
Index: src/jtag/tcl.c
===================================================================
--- src/jtag/tcl.c (revision 2714)
+++ src/jtag/tcl.c (working copy)
@@ -845,6 +845,14 @@
int tmp = 0;
int m;
+ m = RESET_SRST_GATES_JTAG;
+ tmp = 0;
+ if (strcmp(*args, "srst_gates_jtag") == 0)
+ {
+ tmp = RESET_SRST_GATES_JTAG;
+ goto next;
+ }
+
/* signals */
m = RESET_HAS_TRST | RESET_HAS_SRST;
if (strcmp(*args, "none") == 0)
Index: doc/openocd.texi
===================================================================
--- doc/openocd.texi (revision 2719)
+++ doc/openocd.texi (working copy)
@@ -2018,6 +2018,10 @@
@option{combined} implies both @option{srst_pulls_trst} and
@option{trst_pulls_srst}.
+...@option{srst_gates_jtag} indicates that asserting SRST gates the
+JTAG clock. This means that no communication can happen on JTAG
+while SRST is asserted.
+
The optional @var{trst_type} and @var{srst_type} parameters allow the
driver mode of each reset line to be specified. These values only affect
JTAG interfaces with support for different driver modes, like the Amontec
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