For testing and comments
This patch adds :
int cortex_a8_assert_reset(target_t *target);
int cortex_a8_deassert_reset(target_t *target);
Full testing is hard to do with the BeagleBoard since there are
no SRST or TRST, but this brings reset handling closer to standard
OpenOCD (as confusing as this is)
On my BeagleBoard I can now do "reset halt" and end up somwhere
in the X-Loader.
Best regards,
Magnus
Index: src/target/cortex_a8.c
===================================================================
--- src/target/cortex_a8.c (revision 2788)
+++ src/target/cortex_a8.c (working copy)
@@ -67,6 +67,8 @@
uint32_t *value, int regnum);
int cortex_a8_dap_write_coreregister_u32(target_t *target,
uint32_t value, int regnum);
+int cortex_a8_assert_reset(target_t *target);
+int cortex_a8_deassert_reset(target_t *target);
target_type_t cortexa8_target =
{
@@ -81,8 +83,8 @@
.resume = cortex_a8_resume,
.step = cortex_a8_step,
- .assert_reset = NULL,
- .deassert_reset = NULL,
+ .assert_reset = cortex_a8_assert_reset,
+ .deassert_reset = cortex_a8_deassert_reset,
.soft_reset_halt = NULL,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
@@ -1188,7 +1190,51 @@
* Cortex-A8 Reset fuctions
*/
+int cortex_a8_assert_reset(target_t *target)
+{
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+ LOG_DEBUG(" ");
+
+ if (jtag_reset_config & RESET_HAS_SRST)
+ {
+ /* default to asserting srst */
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ {
+ jtag_add_reset(1, 1);
+ }
+ else
+ {
+ jtag_add_reset(0, 1);
+ }
+ }
+
+ /* registers are now invalid */
+ armv4_5_invalidate_core_regs(target);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
+
+int cortex_a8_deassert_reset(target_t *target)
+{
+
+ LOG_DEBUG(" ");
+
+ /* deassert reset lines */
+ jtag_add_reset(0, 0);
+
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target)) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
/*
* Cortex-A8 Memory access
*
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