arm11 has a bug in that you cannot at the same time assert srst to the arm11 core and access its JTAG logic. Asserting srst will disable TAP logic.
My guess is that flops' reset pin in JTAG core are connected to srst. It is unclear to me how long you have to wait after reset before accessing JTAG. It looks like srst puts JTAG logic into power-on-reset state. There is another bug in the arm11 core. When you generate an access to external logic (for example ddr controller via AHB bus) and that block is not configured (perhaps it is still held in reset), that transaction will never complete. This will hang arm11 core but it will also hang JTAG controller. Nothing, short of srst assertion will bring it out of this. Hope this helps. On Tue, 2009-10-13 at 14:34 +0200, Øyvind Harboe wrote: > Can someone help me explain what the effects of asserting > srst on an arm11 is? > > Does anyone know how to safely reset an arm11 into the > halted state? > > I've been trying to read the arm11 documentation and tinkering > with the OpenOCD arm11 code against an iMX31, without > becoming a whole lot wiser... > > It appears, minimally, that srst messes with the TAP state... > _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
