I made the "dap info" output more comprehensible; samples below.
Basically, remove garbage (including CID constants) and interpret
the part number plus, where relevant, CoreSight type.
The patch is ugly; if you want to see it, it's in git now.
Only changes output, except for reading that CoreSight type
code, so it's not going to break anything.
- Dave
Cortex-M3 (Stellaris):
======================
> dap info
ap identification register 0x14770011
Type is mem-ap AHB
ap debugbase 0xe00ff003
Valid ROM table present
MEMTYPE system memory present on bus
ROMTABLE[0x0] = 0xfff0f003
Component base address 0xe000e000, start address 0xe000e000
Component class is 0xe, Generic IP component
Peripheral ID[4..0] = hex 04 00 1b b0 00
Part is Cortex-M3 NVIC (Interrupt Controller)
ROMTABLE[0x4] = 0xfff02003
Component base address 0xe0001000, start address 0xe0001000
Component class is 0xe, Generic IP component
Peripheral ID[4..0] = hex 04 00 1b b0 02
Part is Cortex-M3 DWT (Data Watchpoint and Trace)
ROMTABLE[0x8] = 0xfff03003
Component base address 0xe0002000, start address 0xe0002000
Component class is 0xe, Generic IP component
Peripheral ID[4..0] = hex 04 00 0b b0 03
Part is Cortex-M3 FBP (Flash Patch and Breakpoint)
ROMTABLE[0xc] = 0xfff01003
Component base address 0xe0000000, start address 0xe0000000
Component class is 0xe, Generic IP component
Peripheral ID[4..0] = hex 04 00 1b b0 01
Part is Cortex-M3 ITM (Instrumentation Trace Module)
ROMTABLE[0x10] = 0xfff41003
Component base address 0xe0040000, start address 0xe0040000
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
Peripheral ID[4..0] = hex 04 00 1b b9 23
Part is Cortex-M3 TPIU (Trace Port Interface Unit)
ROMTABLE[0x14] = 0xfff42002
Component not present
ROMTABLE[0x18] = 0x0
End of ROM table
>
Cortex-A8 (Beagleboard):
========================
> dap info 1
ap identification register 0x04770002
Type is mem-ap APB
ap debugbase 0x80000000
ROM table in legacy format
MEMTYPE System memory not present. Dedicated debug bus.
ROMTABLE[0x0] = 0xd4010003
Component base address 0x54010000, start address 0x54010000
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Peripheral ID[4..0] = hex 04 10 2b b9 21
Part is Cortex-A8 ETM (Embedded Trace)
ROMTABLE[0x4] = 0xd4011003
Component base address 0x54011000, start address 0x54011000
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Peripheral ID[4..0] = hex 04 10 2b bc 08
Part is Cortex-A8 Debug (Debug Unit)
ROMTABLE[0x8] = 0xd4012003
Component base address 0x54012000, start address 0x54012000
Component class is 0x9, CoreSight component
Type is 0x64, Debug Control, Reserved
Peripheral ID[4..0] = hex 00 00 09 71 13
Part is -*- unrecognized -*-
ROMTABLE[0xc] = 0xd4013002
Component not present
ROMTABLE[0x10] = 0xd4019003
Component base address 0x54019000, start address 0x54019000
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
Peripheral ID[4..0] = hex 04 00 1b b9 12
Part is Coresight TPIU (Trace Port Interface Unit)
ROMTABLE[0x14] = 0xd401b003
Component base address 0x5401b000, start address 0x5401b000
Component class is 0x9, CoreSight component
Type is 0x21, Trace Sink, Buffer
Peripheral ID[4..0] = hex 04 00 0b b9 07
Part is Coresight ETB (Trace Buffer)
ROMTABLE[0x18] = 0xd401d003
Component base address 0x5401d000, start address 0x5401d000
Component class is 0xf, PrimeCell or System component
Peripheral ID[4..0] = hex 00 00 09 73 43
Part is TI DAPCTL
ROMTABLE[0x1c] = 0xd4500003
Component base address 0x54500000, start address 0x54500000
Component class is 0x9, CoreSight component
Type is 0x63, Trace Source, Reserved
Peripheral ID[4..0] = hex 00 00 19 71 20
Part is TI SDTI (System Debug Trace Interface)
ROMTABLE[0x20] = 0x0
End of ROM table
>
_______________________________________________
Openocd-development mailing list
[email protected]
https://lists.berlios.de/mailman/listinfo/openocd-development
