Hi Rolf,
****************
Following commands are called on reset_init:
## -- Event handlers --
proc reset_init { } {
jtag_khz 200
# Force target into ARM state
armv4_5 core_state arm
# -- 1. Disconnect the PLL with one feed sequence if PLL is already
connected. --
# - PLLCON (0xE01FC080) = 1
mww 0xE01FC080 0x00000001
# - PLLFEED (0xE01FC08C) sequence -
mww 0xE01FC08C 0x000000AA
mww 0xE01FC08C 0x00000055
# -- 2. Disable the PLL with one feed sequence. --
# - PLLCON = 0
mww 0xE01FC080 0x00000000
# - PLLFEED sequence -
mww 0xE01FC08C 0x000000AA
mww 0xE01FC08C 0x00000055
# -- 3. Enable main oscillator. --
# - SCS = 0x20 (OSCEN = 1)
mww 0xE01FC1A0 0x00000020
# -- 4. Clock Source Selection Control register set clock source to PLL
to be main osc. 12MHz --
# - CLKSRCSEL (0xE01FC10C) = 1
mww 0xE01FC10C 0x00000001
# -- 5. Write to the PLLCFG and make it effective with one feed
sequence. The PLLCFG can
# only be updated when the PLL is disabled. --
# - PLLCFG (0xE01FC084) = M is set to 1 N is set to 12
mww 0xE01FC084 0x0000000B
# - PLLFEED sequence -
mww 0xE01FC08C 0x000000AA
mww 0xE01FC08C 0x00000055
# -- 6. Enable the PLL with one feed sequence. --
# - PLLCON (0xE01FC080) = 1
mww 0xE01FC080 0x00000001
# - PLLFEED sequence -
mww 0xE01FC08C 0x000000AA
mww 0xE01FC08C 0x00000055
# -- 7. Change the CPU Clock Divider setting for the operation with the
PLL. It's critical to do
# this before connecting the PLL. --
# - CCLKCFG (0xE01FC104) = 5 (Fcpu = 288/6 = 48MHz )
mww 0xE01FC104 0x00000005
# -- 8. Wait for the PLL to lock
sleep 200
# -- 9. Connect PLL with One Feed Seq --
# - PLLCON = 3
mww 0xE01FC080 0x00000003
# - PLLFEED sequence -
mww 0xE01FC08C 0x000000AA
mww 0xE01FC08C 0x00000055
# -- 10. Wait for the PLL to connect
sleep 100
# Do not remap 0x0000-0x0020 to anything but the Flash
mwb 0xE01FC040 0x01
## now setup GPIO PINS for the External Static Memory controller
#setup pins for addr / databus
#PINSEL6 sets up D0-15
mww 0xE002C018 0x55555555
#PINSEL8 sets up A0-15
mww 0xE002C020 0x55555555
#PINSEL9 sets up A16-23, BLS and OE + WE
mww 0xE002C024 0x55555555
# Enable EMC(bit 11) in PCON register
#mww 0xE01FC0C4 0x00000800 #Default ON
## setup the EMC for CS 0
#EMC Control, enable EMC, and set normal Memmap
mww 0xFFE08000 0x00000001
#EMCStaticConfig0 :
# MW : 16bit
# PB : 1
mww 0xFFE08200 0x00000081
#EMCStaticWaitWr and #EMCStaticWaitRd are left to their defaults for now
#speed up jtag clk again
#jtag_rclk 500
jtag_rclk 2000
}
****************
Including this:
mww 0xFFE08200 0x00000081
Which I believe to be what you mention?
********Some other parts of the script looks like this: *********
# LPC2000 -> SRST causes TRST
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4
# LPC2468 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000
-work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init { reset_init }
gdb_memory_map enable
gdb_flash_program enable
proc deif_flash_external {IMGFILE} {
reset init
halt
sleep 100
poll
flash protect_check 1
flash protect 1 0 2047 off
flash write_image $IMGFILE 0x80000000
reset
shutdown
}
# LPC2468 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# After reset the chip uses its internal 4MHz RC oscillator.
flash bank lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 24000 calc_checksum
flash bank cfi 0x80000000 0x800000 2 2 $_TARGETNAME jedec_probe
# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 =
666kHz, so use 500.
#jtag_rclk 500
fast enable
debug_level 2
init
****************
I made the "proc deif_flash_external"
The "proc reset_init" is translated from something that works on Lauterbach
with this board.
****************Here is the full log: ****************
Z:\RB-RC1\build\bgcf-pt2>set filename=Z:\RB-RC1\build\bgcf-pt2\bgcfapp.bin
Z:\RB-RC1\build\bgcf-pt2>rem echo.Z:\RB-RC1\build\bgcf-pt2\bgcfapp.bin
Z:\RB-RC1\build\bgcf-pt2>cd "C:\Program Files\OpenOCD\0.3.1\bin\"
Z:\RB-RC1\build\bgcf-pt2>set filename=Z:\\RB-RC1\\build\\bgcf-pt2\\bgcfapp.bin
Z:\RB-RC1\build\bgcf-pt2>rem echo.Z:\\RB-RC1\\build\\bgcf-pt2\\bgcfapp.bin
Z:\RB-RC1\build\bgcf-pt2>openOCD.exe -f "C:\Program Files\OpenOCD\0.3.1\interfac
e\jtagkey.cfg" -f "C:\Program Files\OpenOCD\0.3.1\target\lpc2468.cfg" -c "deif_
flash_external Z:\\RB-RC1\\build\\bgcf-pt2\\bgcfapp.bin"
Open On-Chip Debugger 0.3.1 (2009-12-12-01:07)
$URL$
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
500 kHz
User : 12 15 command.c:400 command_print(): debug_level: 3
Debug: 14 15 command.c:68 script_debug(): command - jtag_nsrst_delay
Debug: 15 15 command.c:77 script_debug(): jtag_nsrst_delay - argv[0]=ocd_jtag_ns
rst_delay
Debug: 16 15 command.c:77 script_debug(): jtag_nsrst_delay - argv[1]=100
User : 17 15 command.c:400 command_print(): jtag_nsrst_delay: 100
Debug: 19 15 command.c:68 script_debug(): command - jtag_ntrst_delay
Debug: 20 15 command.c:77 script_debug(): jtag_ntrst_delay - argv[0]=ocd_jtag_nt
rst_delay
Debug: 21 15 command.c:77 script_debug(): jtag_ntrst_delay - argv[1]=100
User : 22 15 command.c:400 command_print(): jtag_ntrst_delay: 100
Debug: 24 15 command.c:68 script_debug(): command - jtag_khz
Debug: 25 15 command.c:77 script_debug(): jtag_khz - argv[0]=ocd_jtag_khz
Debug: 26 31 command.c:77 script_debug(): jtag_khz - argv[1]=3000
Debug: 27 31 core.c:1581 jtag_config_khz(): handle jtag khz
Debug: 28 31 core.c:1537 jtag_khz_to_speed(): convert khz to interface specific
speed value
User : 29 31 command.c:400 command_print(): 3000 kHz
Debug: 31 31 command.c:68 script_debug(): command - reset_config
Debug: 32 31 command.c:77 script_debug(): reset_config - argv[0]=ocd_reset_confi
g
Debug: 33 31 command.c:77 script_debug(): reset_config - argv[1]=trst_and_srst
Debug: 34 31 command.c:77 script_debug(): reset_config - argv[2]=srst_pulls_trst
User : 35 31 command.c:400 command_print(): trst_and_srst srst_pulls_trst srst_g
ates_jtag trst_push_pull srst_open_drain
Debug: 36 47 tcl.c:245 jim_newtap_cmd(): Creating New Tap, Chip: lpc2468, Tap: c
pu, Dotted: lpc2468.cpu, 8 params
Debug: 37 47 tcl.c:262 jim_newtap_cmd(): Processing option: -irlen
Debug: 38 47 tcl.c:262 jim_newtap_cmd(): Processing option: -ircapture
Debug: 39 47 tcl.c:262 jim_newtap_cmd(): Processing option: -irmask
Debug: 40 47 tcl.c:262 jim_newtap_cmd(): Processing option: -expected-id
Debug: 41 47 core.c:1314 jtag_tap_init(): Created Tap: lpc2468.cpu @ abs positio
n 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 42 47 target.c:4515 jim_target(): Target command params:
Debug: 43 47 target.c:4516 jim_target(): target create lpc2468.cpu arm7tdmi -end
ian little -chain-position lpc2468.cpu -variant arm7tdmi-s_r4
Debug: 45 62 command.c:68 script_debug(): command - gdb_memory_map
Debug: 46 62 command.c:77 script_debug(): gdb_memory_map - argv[0]=ocd_gdb_memor
y_map
Debug: 47 62 command.c:77 script_debug(): gdb_memory_map - argv[1]=enable
Debug: 49 62 command.c:68 script_debug(): command - gdb_flash_program
Debug: 50 62 command.c:77 script_debug(): gdb_flash_program - argv[0]=ocd_gdb_fl
ash_program
Debug: 51 62 command.c:77 script_debug(): gdb_flash_program - argv[1]=enable
Debug: 53 62 command.c:68 script_debug(): command - bank
Debug: 54 62 command.c:77 script_debug(): bank - argv[0]=ocd_flash_bank
Debug: 55 62 command.c:77 script_debug(): bank - argv[1]=lpc2000
Debug: 56 78 command.c:77 script_debug(): bank - argv[2]=0x0
Debug: 57 78 command.c:77 script_debug(): bank - argv[3]=0x7D000
Debug: 58 78 command.c:77 script_debug(): bank - argv[4]=0
Debug: 59 78 command.c:77 script_debug(): bank - argv[5]=0
Debug: 60 78 command.c:77 script_debug(): bank - argv[6]=lpc2468.cpu
Debug: 61 78 command.c:77 script_debug(): bank - argv[7]=lpc2000_v2
Debug: 62 78 command.c:77 script_debug(): bank - argv[8]=24000
Debug: 63 78 command.c:77 script_debug(): bank - argv[9]=calc_checksum
Debug: 65 78 command.c:68 script_debug(): command - bank
Debug: 66 78 command.c:77 script_debug(): bank - argv[0]=ocd_flash_bank
Debug: 67 93 command.c:77 script_debug(): bank - argv[1]=cfi
Debug: 68 93 command.c:77 script_debug(): bank - argv[2]=0x80000000
Debug: 69 93 command.c:77 script_debug(): bank - argv[3]=0x800000
Debug: 70 93 command.c:77 script_debug(): bank - argv[4]=2
Debug: 71 93 command.c:77 script_debug(): bank - argv[5]=2
Debug: 72 93 command.c:77 script_debug(): bank - argv[6]=lpc2468.cpu
Debug: 73 93 command.c:77 script_debug(): bank - argv[7]=jedec_probe
Debug: 75 93 command.c:68 script_debug(): command - fast
Debug: 76 93 command.c:77 script_debug(): fast - argv[0]=ocd_fast
Debug: 77 93 command.c:77 script_debug(): fast - argv[1]=enable
Debug: 79 93 command.c:68 script_debug(): command - debug_level
Debug: 80 109 command.c:77 script_debug(): debug_level - argv[0]=ocd_debug_level
Debug: 81 109 command.c:77 script_debug(): debug_level - argv[1]=2
debug_level: 2
Info : clock speed 3000 kHz
Info : JTAG tap: lpc2468.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf
1f0, ver: 0x4)
Info : Embedded ICE version 7
Error: EmbeddedICE v7 handling might be broken
target state: halted
target halted in ARM state due to breakpoint, current mode: Undefined
cpsr: 0x700000db pc: 0xa001dd58
Info : JTAG tap: lpc2468.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf
1f0, ver: 0x4)
Warn : srst pulls trst - can not reset into halted mode. Issuing halt after rese
t.
target state: halted
target halted in ARM state due to debug-request, current mode: Undefined
cpsr: 0x300000db pc: 0xa0000558
200 kHz
core state: ARM
RCLK not supported - fallback to 2000 kHz
background polling: on
TAP: lpc2468.cpu (enabled)
target state: halted
target halted in ARM state due to debug-request, current mode: Undefined
cpsr: 0x300000db pc: 0xa0000558
Info : Flash Manufacturer/Device: 0x00bf 0x236d
successfully checked protect state
Error: protect: cfi primary command set 2 unsupported
cleared protection for sectors 0 through 2047 on flash bank 1
Error: timed out while waiting for target halted
Error: error writing to flash at address 0x80000000 at offset 0x00000000 (-902)
Z:\RB-RC1\build\bgcf-pt2>pause
Press any key to continue . . .
****************
The " Error: protect: cfi primary command set 2 unsupported" message only
appears when I run the protect command in the script.
****************
The mww commands are not logged?
Does this make any sense? Or is the error hidden somewhere in the log?
Regards Flemming
-----Original Message-----
From: Rolf Meeser [mailto:rolfm_...@yahoo.de]
Sent: 30. december 2009 13:37
To: openocd-development@lists.berlios.de; Flemming Futtrup
Subject: AW: [Openocd-development] Adding support for SST 39VF6401B external
flash
Hi Flemming,
--- Flemming Futtrup <f...@deif.com> schrieb am Mi, 30.12.2009:
> I have run into trouble with a new board holding the SST
> 39VF6401B external flash.
>
>
> TAP: lpc2468.cpu (enabled)
>
Make sure the buffering is disabled in EMCStaticConfig0 of the LPC2468 (board
config file?).
If enabled, the target algorithm cannot detect the end of the program cycle,
and will wait in an endless loop until a timeout occurs.
> At this point I assumed that the concerned Flash device is
> a NON_CFI device.
>
The reason to declare this device as NON-CFI is that it doesn't work with the
DQ5 polling mode. This mode is standard for CFI devices in cfi.c. Probably it
would be cleaner to define a new fixup function in cfi.c, but the approach with
non_cfi.c should work fine for your device.
> First of all there was no support for this flash in the
> non_cfi.c so I added this:
>
> {
> .mfr = CFI_MFR_SST,
> .id = 0x236d,
> /* SST39VF6401B */
> .pri_id = 0x02,
> .dev_size = 8*MB,
> .interface_desc = 0x2, /* x8 or x16 device
> with BYTE */
> .max_buf_write_size = 0x0,
> .status_poll_mask = CFI_STATUS_POLL_MASK_DQ6_DQ7,
> .num_erase_regions = 1,
> .erase_region_info =
> {
> ERASE_REGION(2048, 4*KB)
> }
> },
>
That's ok.
> Then I added this line to the cfi.c cfi_0002_fixups array:
>
> {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses,
> &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
>
Looks ok, but probably this is already the default, so your fixup won't change
anything.
If the buffer bit is not the problem, it will help to see the debug output
('-d' switch).
Regards,
Rolf
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