On Monday 28 December 2009, Øyvind Harboe wrote: > I'm not quite up to speed on the SWD stuff yet, but I want > to follow this closely enough that I can implement hardware > acceleration of the SWD protocol on the ZY1000(an embedded > OpenOCD host).
My l33t mind-reading powers have improved. I knew you were going to say that! ;) > What embedded hosts offers is very low processing power(on par > with an arm7/9 or so), but also very low latency. I'm thinking > the very low latency could easily be a huge advantage > with the SWD protocol and I'm curious how the upcoming > SWD OpenOCD stack will ensure acceptable performance > with long latency devices. I'm looking specifically at an FT2232 based link that I have in hand. Looks like the main issue will be making sure that the ADIv5.c stuff makes effective use of what it calls the TRANS_MODE_COMPOSITE mode ... which also speeds performance going through JTAG. That is, the way to do this with an FT2232 involves more or less just a GPIO control whether SWDIO connects to MOSI as output, or MISO as input. That switches with no round-trip. > So far we've seen huge disruptive patches that didn't fit > naturally with OpenOCD It'll be a significant evolution, since SWD != JTAG. Many things will need to change. But agreed, they should not be as disruptive as those patches were . > and for something like SWD, I > think we want more speed than haste when committing it. As in, "If you don't have the time to do it right, how will you find the time to do it over?" :) - Dave _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
