I'm trying to get openOCD to work with the PNX8009. It was originally developed by NXP, but is now manufactured by DSPG. The only non-NDA'd info I can find is mcuol.com/download/upfile/75016086.pdf
I'm having trouble getting a usable datasheet from DSPG, so I'm flying a
little blind. What I've done so far is gently modify the LPC29xx file
(which is also ARM968E) to try and work with the PNX8009.
When I run it, the output is:
$ src/openocd -s tcl -f src/CM15.cfg
Open On-Chip Debugger 0.4.0-rc1-dev-00154-g3172be8 (2010-01-28-01:37)
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
done with olimex setup
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled
dcc downloads are enabled
Done with chip setup
Info : device: 4 "2232C"
Info : deviceID: 364511235
Info : SerialNumber: FTSAMY9SA
Info : Description: Olimex OpenOCD JTAG A
Info : clock speed 6000 kHz
Info : TAP pnx8009.cpu does not have IDCODE
Warn : JTAG tap: pnx8009.cpu UNEXPECTED: 0x00000000 (mfg: 0x000,
part: 0x0000, ver: 0x0)
Error: JTAG tap: pnx8009.cpu expected 1 of 1: 0x0596802b (mfg: 0x015,
part: 0x5968, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Info : Embedded ICE version 6
Info : pnx8009.cpu: hardware has 2 breakpoint/watchpoint units
The big problem that I'm having (aside from whatever the above error
messages are telling me) is that I'm getting some single-bit errors when
I try to dump the FLASH memory.
I use the command
Dump_image dumpfile 0 262144
If I run the dump multiple times, I'll get approximately 1000 errors,
almost all of which are a single bit flip (either way)
The config files:
>>>>>>>>>>>>Top.cfg:
source [find interface/olimex-arm-usb-ocd.cfg]
echo "done with olimex setup"
source [find cpu/arm/arm966.tcl]
# @@@ SWAG - see lpc2900
set FLASH_CLOCK 1000
#set HAS_ETB :w
source [find target/pnx8009.cfg]
echo "Done with chip setup"
>>>>>>>>>>>>>>pnx8009.cfg:
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME pnx8009
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0596802B
}
# I think it should be 0x15900f0f
if { [info exists HAS_ETB ] } {
} else {
# Set default (no ETB).
# Show a warning, because this should have been configured
explicitely.
set HAS_ETB 0
# TODO warning?
}
if { [info exists ETBTAPID ] } {
set _ETBTAPID $ETBTAPID
} else {
set _ETBTAPID 0x1B900F0F
}
# TRST and SRST both exist, and can be controlled independently
reset_config trst_and_srst separate
# Define the _TARGETNAME
set _TARGETNAME $_CHIPNAME.cpu
# Include the ETB tap controller if asked for.
# Has to be done manually for newer devices (not an "old" LPC2917/2919).
if { $HAS_ETB == 1 } {
# Clear the HAS_ETB flag. Must be set again for a new tap in the
chain.
set HAS_ETB 0
# Add the ETB tap controller and the ARM9 core debug tap
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_ETBTAPID
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position
$_TARGETNAME -variant arm966e
# Configure ETM and ETB
etm config $_TARGETNAME 8 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
} else {
# Add the ARM9 core debug tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position
$_TARGETNAME -variant arm966e
}
arm7_9 dbgrq enable
arm7_9 dcc_downloads enable
# Flash bank configuration:
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock
(CLK_SYS_FMC) in kHz>
# Flash base address, total flash size, and number of sectors are all
configured automatically.
set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME pnx8009 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
Thanks!
---------------------------
Todd Krein
Director of Architecture
650-566-6657
todd.kr...@ooma.com <mailto:todd.kr...@ooma.com>
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