Hi Todd,

--- Todd Krein <todd.kr...@ooma.com> schrieb am Mi, 10.2.2010:

> I’m trying to understand the relationship between the scan chain
> in the ARM968E core and the rest of the system scan chains in the
> NXP LPC29xx family.

> I’ve found documentation, from ARM, on the scan chain/TAP controller for > 
> the ARM9E core family, and then from NXP there is information on the 
> internal scan chains required to access FLASH and other systems 
> peripherals. What I don’t understand is the relationship between the 
> two. Are the internal scan chains all sitting off of one of the ARM’s 
> unused chains?

There are two independent TAP controllers on the LPC29xx. One TAP is for access 
to the ARM968E core, the other is for boundary scan and direct flash access. 
The access to both is mutually exclusive, and is controlled by the JTAGSEL pin 
of the device.

The first TAP is the "normal" one, and the one you use with debug tools like 
OpenOCD. There's access to the CPU, the system peripherals and the flash 
through this TAP. Flash access is CPU controlled: A piece of code downloaded to 
RAM does the job.

The second TAP is mainly useful for board production. During final board test 
you select this TAP through JTAGSEL. You can do boundary scan to verify your 
PCB function, and you can use direct flash register access independent of the 
CPU for a fast initial flash programming. The second TAP isn't useful for 
debugging, since you cannot access the CPU through it. You'd rather use the 
first TAP, and do flash programming under CPU control.

Without any JTAG connection, JTAGSEL is usually left at its default (second 
TAP!). This is because it also influences which oscillator is used for system 
startup.

I hope this is at least close to what you've asked for. :-)

Regards,
Rolf


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